| Title | (Invited Paper) Development of Full-HD Multi-standard Video CODEC IP Based on Heterogeneous Multiprocessor Architecture |
| Author | *Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira (Hitachi, Ltd., Japan), Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori (Renesas Technology Corp., Japan) |
| Page | pp. 528 - 534 |
| Keyword | CODEC, video, full-HD, H.264, VC-1 |
| Abstract | To support numerous video codec standards and full-HD videos on different consumer devices, a multi-standard CODEC IP based on a heterogeneous multiprocessor architecture was developed. Operation-specific processors were designed in regards to two types of processing: stream processing and pixel processing. The CODEC also uses effectively several dedicated circuits. To design the CODEC, we developed a C-language model to check our design. The CODEC can process full-HD videos formatted in H.264, MPEG-2, MPEG-4, and VC-1 at 162 MHz operating frequency. |
| Slides |
| Title | (Invited Paper) A 65nm Dual-mode Baseband and Multimedia Application Processor SoC with Advanced Power and Memory Management |
| Author | *Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka (Renesas Technology Corp., Japan) |
| Page | pp. 535 - 539 |
| Keyword | application processor, mobile phone, low power, multi-media, MMU |
| Abstract | A Dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the Partial Clock Activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory footprint by 43MB, sharing external memory among CPUs and HW-IPs using virtual address space that enables reuse of physically fragmented memory. |
| Slides |