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The 14th Asia and South Pacific Design Automation Conference

Session 6A  System Level Simulation and Modeling
Time: 15:55 - 18:00 Wednesday, January 21, 2009
Location: Room 411+412
Chairs: Vincent J Mooney (Georgia Inst. of Tech., United States), Tsuneo Nakata (Fujitsu Laboratories Ltd., Japan)

6A-1 (Time: 15:55 - 16:20)
TitleAutomatic Instrumentation of Embedded Software for High Level Hardware/Software Co-Simulation
AuthorAimen Bouchhima, *Patrice Gerin, Frédéric Pétrot (TIMA Lab., France)
Pagepp. 546 - 551
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6A-2 (Time: 16:20 - 16:45)
TitleFast and Accurate Performance Simulation of Embedded Software for MPSoC
Author*Eric Cheung, Harry Hsieh (Univ. of California, Riverside, United States), Felice Balarin (Cadence Design Systems, United States)
Pagepp. 552 - 557
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6A-3 (Time: 16:45 - 17:10)
TitleAutomatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model
Author*Chen Kang Lo, Ren Song Tsay (National Tsing Hua Univ., Taiwan)
Pagepp. 558 - 563
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6A-4 (Time: 17:10 - 17:35)
TitleA Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor
Author*Farhad Mehdipour (Kyushu Univ., Japan), Hamid Noori (ISIT, Japan), Bahman Javadi (Amirkabir Univ. of Tech., Iran), Hiroaki Honda (ISIT, Japan), Koji Inoue, Kazuaki Murakami (Kyushu Univ., Japan)
Pagepp. 564 - 569
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