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The 14th Asia and South Pacific Design Automation Conference

Session 7B  Sequential Design Verification
Time: 10:15 - 12:20 Thursday, January 22, 2009
Location: Room 413
Chairs: Yosinori Watanabe (Cadence, United States), Chung-Yang Huang (National Taiwan Univ., Taiwan)

7B-1 (Time: 10:15 - 10:40)
TitleDependent Latch Identification in the Reachable State Space
AuthorChen-Hsuan Lin, *Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 630 - 635
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7B-2 (Time: 10:40 - 11:05)
TitleComplete-k-Distinguishability for Retiming and Resynthesis Equivalence Checking without Restricting Synthesis
AuthorNikolaos Liveris, *Hai Zhou (Northwestern Univ., United States), Prithviraj Banerjee (HP Labs, United States)
Pagepp. 636 - 641
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7B-4 (Time: 11:30 - 11:55)
TitleMulti-Clock SVA Synthesis without Re-writing
Author*Jiang Long, Andrew Seawright, Paparao Kavalipati (Mentor Graphics Corp., United States)
Pagepp. 648 - 653
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7B-5 (Time: 11:55 - 12:20)
TitleAutomatic Formal Verification of Clock Domain Crossing Signals
Author*Bing Li, Chris Ka-Kei Kwok (Mentor Graphics Corp., United States)
Pagepp. 654 - 659
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Slides