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The 14th Asia and South Pacific Design Automation Conference

Session 8C  Verification, Test, and Yield
Time: 13:30 - 15:35 Thursday, January 22, 2009
Location: Room 414+415
Chairs: Yasuo Sato (Hitachi, Ltd., Japan), Sudhakar M. Reddy (Univ. of Iowa, United States)

8C-1 (Time: 13:30 - 13:55)
TitleSelf-Adjusting Constrained Random Stimulus Generation Using Splitting Evenness Evaluation and XOR Constraints
AuthorShujun Deng, Zhiqiu Kong, *Jinian Bian, Yanni Zhao (Tsinghua Univ., China)
Pagepp. 769 - 774
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8C-2 (Time: 13:55 - 14:20)
TitleDiagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input
Author*Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang (National Taiwan Univ., Taiwan)
Pagepp. 775 - 780
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8C-3 (Time: 14:20 - 14:45)
TitlePath Selection for Monitoring Unexpected Systematic Timing Effects
Author*Nicholas Callegari, Pouria Bastani, Li-C. Wang (Univ. of California, Santa Barbara, United States), Sreejit Chakravarty, Alexander Tetelbaum (LSI Corp., United States)
Pagepp. 781 - 786
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8C-4 (Time: 14:45 - 15:10)
TitleDesign for Burn-In Test: A Technique for Burn-In Thermal Stability under Die-to-Die Parameter Variations
AuthorMesut Meterelliyoz, *Kaushik Roy (Purdue Univ., United States)
Pagepp. 787 - 792
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8C-5 (Time: 15:10 - 15:35)
TitleTest Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints
Author*Thomas Edison Yu, Tomokazu Yoneda (NAIST, Japan), Krishnendu Chakrabarty (Duke Univ., United States), Hideo Fujiwara (NAIST, Japan)
Pagepp. 793 - 798
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