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The 14th Asia and South Pacific Design Automation Conference

Session 9A  Memory Systems Simulation and Optimization
Time: 15:55 - 18:00 Thursday, January 22, 2009
Location: Room 411+412
Chair: Zonghua Gu (HKUST, Hong Kong)

9A-1 (Time: 15:55 - 16:20)
TitleSoft Lists: A Native Index Structure for NOR-Flash-Based Embedded Devices
Author*Li-Pin Chang, Chen-Hui Hsu (National Chiao Tung Univ., Taiwan)
Pagepp. 799 - 804
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9A-2 (Time: 16:20 - 16:45)
TitleEnergy-aware Register File Re-Partitioning for Clustered VLIW Architectures
Author*Chun Jason Xue, Minming Li, Yingchao Zhao, Bessie Hu (City Univ. of Hong Kong, Hong Kong)
Pagepp. 805 - 810
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9A-3 (Time: 16:45 - 17:10)
TitleMemory Subsystem Simulation in Software TLM/T Models
Author*Eric Cheung, Harry Hsieh (Univ. of California, Riverside, United States), Felice Balarin (Cadence Design Systems, United States)
Pagepp. 811 - 816
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9A-4 (Time: 17:10 - 17:35)
TitleExact and Fast L1 Cache Simulation for Embedded Systems
Author*Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Pagepp. 817 - 822
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Slides

9A-5 (Time: 17:35 - 18:00)
TitleAccuracy-Aware SRAM: A Reconfigurable Low Power SRAM Architecture for Mobile Multimedia Applications
AuthorMinki Cho (Georgia Inst. of Tech., United States), Jason Schlessman (Princeton Univ., United States), *Wayne Wolf, Saibal Mukhopadhyay (Georgia Inst. of Tech., United States)
Pagepp. 823 - 828
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