The 14th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Tuesday, January 20, 2009

A	B	C	D
1K (Small Auditorium, 5F) Opening and Keynote Session I 8:30 - 10:00
1A (Room 411+412) On-Chip Communication Architectures 10:15 - 12:20	1B (Room 413) Dealing with Thermal Issues 10:15 - 12:20	1C (Room 414+415) Advances in Behavioral Synthesis 10:15 - 12:20	1D (Room 416+417) University LSI Design Contest 10:15 - 12:20
2A (Room 411+412) MPSoC and IP Integration 13:30 - 15:35	2B (Room 413) Power Analysis and Optimization 13:30 - 15:35	2C (Room 414+415) Logic and Arithmetic Optimization 13:30 - 15:35	2D (Room 416+417) Special Session: EDA Acceleration Using New Architectures 13:30 - 15:35
3A (Room 411+412) System-Level Design of 3D Chips and Configurable Systems 15:55 - 18:00	3B (Room 413) Advances in Timing Analysis and Modeling 15:55 - 18:00		3D (Room 416+417) Special Session: Hardware Dependent Software for Multi- and Many-Core Embedded Systems 15:55 - 18:00

Wednesday, January 21, 2009

A	B	C	D
2K (Small Auditorium, 5F) Keynote Session II 9:00 - 10:00
4A (Room 411+412) System Level Architectures 10:15 - 12:20	4B (Room 413) Beyond Traditional Floorplanning and Placement 10:15 - 12:20	4C (Room 414+415) Signal/Power Integrity and Simulation 10:15 - 12:20	4D (Room 416+417) Special Session: Challenges in 3D Integrated Circuit Design 10:15 - 12:20
5A (Room 411+412) Energy-Aware System Level Design Methodology 13:30 - 15:35	5B (Room 413) Design for Manufacturing and Reliability 13:30 - 15:35	5C (Room 414+415) Analog, RF and Mixed-Signal CAD 13:30 - 15:35	5D (Room 416+417) Designers' Forum: Consumer SoC 13:30 - 15:35
6A (Room 411+412) System Level Simulation and Modeling 15:55 - 18:00	6B (Room 413) Chip and Package Routing Techniques 15:55 - 18:00		6D (Room 416+417) Designers' Forum: ESL Design Methods 15:55 - 18:00

Thursday, January 22, 2009

A	B	C	D
3K (Small Auditorium, 5F) Keynote Session III 9:00 - 10:00
7A (Room 411+412) Compilation Techniques for Embedded Systems 10:15 - 12:20	7B (Room 413) Sequential Design Verification 10:15 - 12:20	7C (Room 414+415) Scan Test Generation 10:15 - 12:20	7D (Room 416+417) Designers' Forum: Analog/RF Circuit Designs 10:15 - 12:20
8A (Room 411+412) High-Level Design and Scheduling 13:30 - 15:35	8B (Room 413) Emerging Design Methodologies and Applications 13:30 - 15:35	8C (Room 414+415) Verification, Test, and Yield 13:30 - 15:35	8D (Room 416+417) Designers' Forum: Near-Future SoC Architectures -- Can Dynamically Reconfigurable Processors be a Key Technology? 13:30 - 15:35
9A (Room 411+412) Memory Systems Simulation and Optimization 15:55 - 18:00	9B (Room 413) Emerging Technologies 15:55 - 18:00		9D (Room 416+417) Special Session: Dependable VLSI: Device, Design and Architecture -- How should they cooperate ? -- 15:55 - 18:00

List of Papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 20, 2009

Session 1K Opening and Keynote Session I
Time: 8:30 - 10:00 Tuesday, January 20, 2009
Location: Small Auditorium, 5F
Chair: Kazutoshi Wakabayashi (NEC Corp., Japan)

1K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) Challenges to EDA System from the View Point of Processor Design and Technology Drivers
Author	Mitsuo Saito (Toshiba Corp. Semiconductor Company, Japan)
Detailed information (abstract, keywords, etc)

Session 1A On-Chip Communication Architectures
Time: 10:15 - 12:20 Tuesday, January 20, 2009
Location: Room 411+412
Chair: Sri Parameswaran (Univ. of New South Wales, Australia)

1A-1 (Time: 10:15 - 10:40)

Title	Adaptive Inter-router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architectures
Author	Avinash Karanth Kodi (Ohio Univ., United States), Ashwini Sarathy, Ahmed Louri, *Janet Wang (Univ. of Arizona, United States)
Page	pp. 1 - 6
Detailed information (abstract, keywords, etc)
Slides

1A-2 (Time: 10:40 - 11:05)

Title	Analysis of Communication Delay Bounds for Network on Chips
Author	*Yue Qian (National Univ. of Defense Tech., China), Zhonghai Lu (Royal Inst. of Tech., Sweden), Wenhua Dou (National Univ. of Defense Tech., China)
Page	pp. 7 - 12
Detailed information (abstract, keywords, etc)

1A-3 (Time: 11:05 - 11:30)

Title	Frequent Value Compression in Packet-based NoC Architectures
Author	Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, *Jun Yang (Univ. of Pittsburgh, United States), Li Zhao (Intel, United States)
Page	pp. 13 - 18
Detailed information (abstract, keywords, etc)

1A-4 (Time: 11:30 - 11:55)

Title	Simultaneous Data Transfer Routing and Scheduling for Interconnect Minimization in Multicycle Communication Architecture
Author	Yu-Ju Hong (Purdue Univ., United States), Ya-Shih Huang, *Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 19 - 24
Detailed information (abstract, keywords, etc)

1A-5 (Time: 11:55 - 12:20)

Title	Dynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications
Author	Sudeep Pasricha, *Nikil Dutt, Fadi Kurdahi (Univ. of California, Irvine, United States)
Page	pp. 25 - 30
Detailed information (abstract, keywords, etc)

Session 1B Dealing with Thermal Issues
Time: 10:15 - 12:20 Tuesday, January 20, 2009
Location: Room 413
Chairs: Youngsoo Shin (KAIST, Republic of Korea), Li Shang (Univ. of Colorado, Boulder, United States)

1B-1 (Time: 10:15 - 10:40)

Title	Stochastic Thermal Simulation Considering Spatial Correlated Within-Die Process Variations
Author	*Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Page	pp. 31 - 36
Detailed information (abstract, keywords, etc)

1B-2 (Time: 10:40 - 11:05)

Title	A Control Theory Approach for Thermal Balancing of MPSoC
Author	*Francesco Zanini, David Atienza, Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 37 - 42
Detailed information (abstract, keywords, etc)

1B-3 (Time: 11:05 - 11:30)

Title	Thermal Optimization in Multi-Granularity Multi-Core Floorplanning
Author	*Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim (Georgia Inst. of Tech., United States)
Page	pp. 43 - 48
Detailed information (abstract, keywords, etc)

1B-4 (Time: 11:30 - 11:55)

Title	Temperature-Aware Dynamic Frequency and Voltage Scaling for Reliability and Yield Enhancement
Author	*Yu-Wei Yang, Katherine Shu-Min Li (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 49 - 54
Detailed information (abstract, keywords, etc)
Slides

1B-5 (Time: 11:55 - 12:20)

Title	A Multiple Supply Voltage Based Power Reduction Method in 3-D ICs Considering Process Variations and Thermal Effects
Author	Shih-An Yu, *Pei-Yu Huang, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Page	pp. 55 - 60
Detailed information (abstract, keywords, etc)

Session 1C Advances in Behavioral Synthesis
Time: 10:15 - 12:20 Tuesday, January 20, 2009
Location: Room 414+415
Chairs: Shigeru Yamashita (NAIST, Japan), Kiyoung Choi (Seoul National Univ., Republic of Korea)

1C-1 (Time: 10:15 - 10:40)

Title	FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization
Author	*Gregory Lucas, Scott Cromar, Deming Chen (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 61 - 66
Detailed information (abstract, keywords, etc)

1C-2 (Time: 10:40 - 11:05)

Title	CriAS: A Performance-Driven Criticality-Aware Synthesis Flow for On-Chip Multicycle Communication Architecture
Author	*Chia-I Chen, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 67 - 72
Detailed information (abstract, keywords, etc)

1C-3 (Time: 11:05 - 11:30)

Title	Tolerating Process Variations in High-Level Synthesis Using Transparent Latches
Author	*Yibo Chen, Yuan Xie (Pennsylvania State Univ., United States)
Page	pp. 73 - 78
Detailed information (abstract, keywords, etc)

1C-4 (Time: 11:30 - 11:55)

Title	Variation-Aware Resource Sharing and Binding in Behavioral Synthesis
Author	Feng Wang (Qualcomm Inc., United States), Yuan Xie (Pennsylvania State Univ., United States), *Andres Takach (Mentor Graphics Corp., United States)
Page	pp. 79 - 84
Detailed information (abstract, keywords, etc)

1C-5 (Time: 11:55 - 12:20)

Title	Peak Temperature Control in Thermal-aware Behavioral Synthesis through Allocating the Number of Resources
Author	*Junbo Yu, Qiang Zhou, Jinian Bian (Tsinghua Univ., China)
Page	pp. 85 - 90
Detailed information (abstract, keywords, etc)

Session 1D University LSI Design Contest
Time: 10:15 - 12:20 Tuesday, January 20, 2009
Location: Room 416+417
Chairs: Jiun-In Guo (National Chung Cheng Univ., Taiwan), Hiroki Ishikuro (Keio Univ., Japan)

1D-1 (Time: 10:15 - 10:20)

Title	A Wireless Real-Time On-Chip Bus Trace System
Author	*Shusuke Kawai, Takayuki Ikari (Keio Univ., Japan), Yutaka Takikawa (Renesas Design Corp, Japan), Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ., Japan)
Page	pp. 91 - 92
Detailed information (abstract, keywords, etc)
Slides

1D-2 (Time: 10:20 - 10:25)

Title	CKVdd: A Self-Stabilization Ramp-Vdd Technique for Dynamic Power Reduction
Author	Chin-Hsien Wang, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan)
Page	pp. 93 - 94
Detailed information (abstract, keywords, etc)
Slides

1D-3 (Time: 10:25 - 10:30)

Title	A 300 nW, 7 ppm/℃ CMOS Voltage Reference Circuit based on Subthreshold MOSFETs
Author	*Ken Ueno (Hokkaido Univ., Japan), Tetsuya Hirose (Kobe Univ., Japan), Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ., Japan)
Page	pp. 95 - 96
Detailed information (abstract, keywords, etc)
Slides

1D-4 (Time: 10:30 - 10:35)

Title	A 100Mbps, 0.19mW Asynchronous Threshold Detector with DC Power-Free Pulse Discrimination for Impulse UWB Receiver
Author	*Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo, Japan)
Page	pp. 97 - 98
Detailed information (abstract, keywords, etc)
Slides

1D-5 (Time: 10:35 - 10:40)

Title	Low-Power CMOS Transceiver Circuits for 60GHz Band Millimeter-wave Impulse Radio
Author	*Ahmet Oncu, Minoru Fujishima (Univ. of Tokyo, Japan)
Page	pp. 99 - 100
Detailed information (abstract, keywords, etc)
Slides

1D-6 (Time: 10:40 - 10:45)

Title	An Inductor-less MPPT Design for Light Energy Harvesting Systems
Author	Hui Shao, *Chi-Ying Tsui, Wing-Hung Ki (HKUST, Hong Kong)
Page	pp. 101 - 102
Detailed information (abstract, keywords, etc)
Slides

1D-7 (Time: 10:45 - 10:50)

Title	A 1 GHz CMOS Comparator with Dynamic Offset Control Technique
Author	*Xiaolei Zhu (Keio Univ., Japan), Sanroku Tsukamoto (Fujitsu Laboratories Ltd., Japan), Tadahiro Kuroda (Keio Univ., Japan)
Page	pp. 103 - 104
Detailed information (abstract, keywords, etc)
Slides

1D-8 (Time: 10:50 - 10:55)

Title	Circuit Design Using Stripe-Shaped PMELA TFTs on Glass
Author	*Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan)
Page	pp. 105 - 106
Detailed information (abstract, keywords, etc)
Slides

1D-9 (Time: 10:55 - 11:00)

Title	Low Energy Level Converter Design for Sub-V_th Logics
Author	Hui Shao, *Chi-Ying Tsui (HKUST, Hong Kong)
Page	pp. 107 - 108
Detailed information (abstract, keywords, etc)
Slides

1D-10 (Time: 11:00 - 11:05)

Title	A Time-to-Digital Converter with Small Circuitry
Author	Kazuya Shimizu, *Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai (Gunma Univ., Japan), Masao Hotta (Musashi Inst. of Tech., Japan)
Page	pp. 109 - 110
Detailed information (abstract, keywords, etc)
Slides

1D-11 (Time: 11:05 - 11:10)

Title	A V_DD Independent Temperature Sensor Circuit with Scaled CMOS Process
Author	*Hiroki Oshiyama, Toshihiro Matsuda, Kei-ichi Suzuki, Hideyuki Iwata (Toyama Prefectural Univ., Japan), Takashi Ohzone (Dawn Enterprise Co. Ltd., Japan)
Page	pp. 111 - 112
Detailed information (abstract, keywords, etc)
Slides

1D-12 (Time: 11:10 - 11:15)

Title	A Current-mode DC-DC Converter using a Quadratic Slope Compensation Scheme
Author	*Chihiro Kawabata, Yasuhiro Sugimoto (Chuo Univ., Japan)
Page	pp. 113 - 114
Detailed information (abstract, keywords, etc)
Slides

1D-13 (Time: 11:15 - 11:20)

Title	Ultra Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids
Author	*Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li (National Chiao Tung Univ., Taiwan), Chou-Kun Lin (ITRI, STC, Taiwan), Chih-Wei Liu (National Chiao Tung Univ., Taiwan)
Page	pp. 115 - 116
Detailed information (abstract, keywords, etc)
Slides

1D-14 (Time: 11:20 - 11:25)

Title	An 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array with a Photodiode Memory Architecture
Author	Daisaku Seto, *Minoru Watanabe (Shizuoka Univ., Japan)
Page	pp. 117 - 118
Detailed information (abstract, keywords, etc)
Slides

1D-15 (Time: 11:25 - 11:30)

Title	A Low-Power FPGA Based on Autonomous Fine-Grain Power-Gating
Author	*Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ., Japan)
Page	pp. 119 - 120
Detailed information (abstract, keywords, etc)
Slides

1D-16 (Time: 11:30 - 11:35)

Title	A 52-mW 8.29mm² 19-mode LDPC Decoder Chip for Mobile WiMAX Applications
Author	*Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu (Andy) Wu (National Taiwan Univ., Taiwan)
Page	pp. 121 - 122
Detailed information (abstract, keywords, etc)
Slides

1D-17 (Time: 11:35 - 11:40)

Title	A Full-Synthesizable High-Precision Built-In Delay Time Measurement Circuit
Author	Ming-Chien Tsai, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan)
Page	pp. 123 - 124
Detailed information (abstract, keywords, etc)
Slides

1D-18 (Time: 11:40 - 11:45)

Title	A Dynamic Quality-Scalable H.264 Video Encoder Chip
Author	*Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen (National Chung Cheng Univ., Taiwan), Ching-Lung Su (National Yunlin Univ. of Science and Tech., Taiwan), Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang (National Chung Cheng Univ., Taiwan)
Page	pp. 125 - 126
Detailed information (abstract, keywords, etc)
Slides

1D-19 (Time: 11:45 - 11:50)

Title	A High Performance LDPC Decoder for IEEE802.11n Standard
Author	*Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto (Waseda Univ., Japan)
Page	pp. 127 - 128
Detailed information (abstract, keywords, etc)
Slides

1D-20 (Time: 11:50 - 11:55)

Title	Design and Chip Implementation of the Ubiquitous Processor HCgorilla
Author	*Masa-aki Fukase, Kazunori Noda, Atsuko Yokoyama, Tomoaki Sato (Hirosaki Univ., Japan)
Page	pp. 129 - 130
Detailed information (abstract, keywords, etc)
Slides

1D-21 (Time: 11:55 - 12:00)

Title	An 8.69 Mvertices/s 278 Mpixels/s Tile-based 3D Graphics SoC HW/SW Development for Consumer Electronics
Author	*Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 131 - 132
Detailed information (abstract, keywords, etc)
Slides

1D-22 (Time: 12:00 - 12:05)

Title	A Multi-Task-Oriented Security Processing Architecture with Powerful Extensibility
Author	*Dan Cao, Jun Han, Xiao-yang Zeng, Shi-ting Lu (Fudan Univ., China)
Page	pp. 133 - 134
Detailed information (abstract, keywords, etc)
Slides

1D-23 (Time: 12:05 - 12:10)

Title	A Delay-Optimized Universal FPGA Routing Architecture
Author	*Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong (Fudan Univ., China)
Page	pp. 135 - 136
Detailed information (abstract, keywords, etc)
Slides

Session 2A MPSoC and IP Integration
Time: 13:30 - 15:35 Tuesday, January 20, 2009
Location: Room 411+412
Chairs: Nozomu Togawa (Waseda Univ., Japan), Marcello Lajolo (NEC Laboratories America, United States)

2A-1 (Time: 13:30 - 13:55)

Title	Timing Variation-Aware Task Scheduling and Binding for MPSoC
Author	*HaNeul Chon, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 137 - 142
Detailed information (abstract, keywords, etc)

2A-2 (Time: 13:55 - 14:20)

Title	Flexible and Abstract Communication and Interconnect Modeling for MPSoC
Author	*Katalin Popovici (TIMA Lab., France), Ahmed Jerraya (CEA-LETI, Minatec, France)
Page	pp. 143 - 148
Detailed information (abstract, keywords, etc)
Slides

2A-3 (Time: 14:20 - 14:45)

Title	Partial Order Method for Timed Simulation of System-Level MPSoC Designs
Author	*Eric Cheung, Harry Hsieh (Univ. of California, Riverside, United States), Felice Balarin (Cadence Design Systems, United States)
Page	pp. 149 - 154
Detailed information (abstract, keywords, etc)

2A-4 (Time: 14:45 - 15:10)

Title	A UML-Based Approach for Heterogeneous IP Integration
Author	*Zhenxin Sun, Weng-Fai Wong (National Univ. of Singapore, Singapore)
Page	pp. 155 - 160
Detailed information (abstract, keywords, etc)
Slides

Session 2B Power Analysis and Optimization
Time: 13:30 - 15:35 Tuesday, January 20, 2009
Location: Room 413
Chair: Masanori Hashimoto (Osaka Univ., Japan)

2B-1 (Time: 13:30 - 13:55)

Title	Statistical Modeling and Analysis of Chip-Level Leakage Power by Spectral Stochastic Method
Author	Ruijing Shen, Ning Mi, *Sheldon Tan (Univ. of California, Riverside, United States), Yici Cai, Xianlong Hong (Tsinghua Univ., China)
Page	pp. 161 - 166
Detailed information (abstract, keywords, etc)

2B-2 (Time: 13:55 - 14:20)

Title	On the Futility of Statistical Power Optimization
Author	Jason Cong, Puneet Gupta, *John Lee (Univ. of California, Los Angeles, United States)
Page	pp. 167 - 172
Detailed information (abstract, keywords, etc)
Slides

2B-3 (Time: 14:20 - 14:45)

Title	Timing Driven Power Gating in High-Level Synthesis
Author	Shih-Hsu Huang, *Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan)
Page	pp. 173 - 178
Detailed information (abstract, keywords, etc)
Slides

2B-4 (Time: 14:45 - 15:10)

Title	Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors
Author	Pingqiang Zhou, Karthikk Sridharan, *Sachin S. Sapatnekar (Univ. of Minnesota, United States)
Page	pp. 179 - 184
Detailed information (abstract, keywords, etc)
Slides

2B-5 (Time: 15:10 - 15:35)

Title	Incremental and On-demand Random Walk for Iterative Power Distribution Network Analysis
Author	*Yiyu Shi, Wei Yao (Univ. of California, Los Angeles, United States), Jinjun Xiong (IBM, United States), Lei He (Univ. of California, Los Angeles, United States)
Page	pp. 185 - 190
Detailed information (abstract, keywords, etc)

Session 2C Logic and Arithmetic Optimization
Time: 13:30 - 15:35 Tuesday, January 20, 2009
Location: Room 414+415
Chairs: Dale Edwards (Semiconductor Research Corp., United States), Hiroyuki Higuchi (Fujitsu Microelectronics Ltd., Japan)

2C-1 (Time: 13:30 - 13:55)

Title	SAT-Controlled Redundancy Addition and Removal --- A Novel Circuit Restructuring Technique
Author	Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, *Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Page	pp. 191 - 196
Detailed information (abstract, keywords, etc)

2C-2 (Time: 13:55 - 14:20)

Title	On Improved Scheme for Digital Circuit Rewiring and Application on Further Improving FPGA Technology Mapping
Author	Fu Shing Chim, *Tak Kei Lam, Yu Liang Wu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 197 - 202
Detailed information (abstract, keywords, etc)
Slides

2C-3 (Time: 14:20 - 14:45)

Title	Hybrid LZA: A Near Optimal Implementation of the Leading Zero Anticipator
Author	Amit Verma (National Inst. of Tech., Rourkela, India), *Ajay K. Verma, Philip Brisk, Paolo Ienne (EPFL, Switzerland)
Page	pp. 203 - 209
Detailed information (abstract, keywords, etc)

2C-4 (Time: 14:45 - 15:10)

Title	An Optimized Design for Serial-Parallel Finite Field Multiplication over GF(2^m) Based on All-One Polynomials
Author	Pramod Kumar Meher (Nanyang Technological Univ., Singapore), *Yajun Ha (National Univ. of Singapore, Singapore), Chiou-Yng Lee (Lunghwa Univ. of Science and Tech., Taiwan)
Page	pp. 210 - 215
Detailed information (abstract, keywords, etc)

Session 2D Special Session: EDA Acceleration Using New Architectures
Time: 13:30 - 15:35 Tuesday, January 20, 2009
Location: Room 416+417
Organizer: Damir A. Jamsek (IBM Corp., United States)

2D-1 (Time: 13:35 - 14:15)

Title	(Invited Paper) Aspects of GPU for General Purpose High Performance Computing
Author	*Reiji Suda (Univ. of Tokyo/JST CREST, Japan), Takayuki Aoki (Tokyo Inst. of Tech./JST CREST, Japan), Shoichi Hirasawa (Univ. of Electro-Communications/JST CREST, Japan), Akira Nukada (Tokyo Inst. of Tech./JST CREST, Japan), Hiroki Honda (Univ. of Electro-Communications/JST CREST, Japan), Satoshi Matsuoka (Tokyo Inst. of Tech./JST CREST/NII, Japan)
Page	pp. 216 - 223
Detailed information (abstract, keywords, etc)

2D-2 (Time: 14:15 - 14:55)

Title	(Invited Paper) Designing and Optimizing Compute Kernels on Nvidia GPUs
Author	*Damir A. Jamsek (IBM Research, United States)
Page	pp. 224 - 229
Detailed information (abstract, keywords, etc)

2D-3 (Time: 14:55 - 15:35)

Title	(Invited Paper) Parallelizing Fundamental Algorithms such as Sorting on Multi-core Processors for EDA Acceleration
Author	*Masato Edahiro (NEC Corp./Univ. of Tokyo, Japan)
Page	pp. 230 - 233
Detailed information (abstract, keywords, etc)
Slides

Session 3A System-Level Design of 3D Chips and Configurable Systems
Time: 15:55 - 18:00 Tuesday, January 20, 2009
Location: Room 411+412
Chairs: Eui-Young Chung (Yonsei Univ., Republic of Korea), Steve Haga (National Sun Yat-Sen Univ.)

3A-1 (Time: 15:55 - 16:20)

Title	System-Level Cost Analysis and Design Exploration for Three-Dimensional Integrated Circuits (3D ICs)
Author	*Xiangyu Dong, Yuan Xie (Pennsylvania State Univ., United States)
Page	pp. 234 - 241
Detailed information (abstract, keywords, etc)

3A-2 (Time: 16:20 - 16:45)

Title	Synthesis of Networks on Chips for 3D Systems on Chips
Author	*Srinivasan Murali, Ciprian Seiculescu (EPFL, Switzerland), Luca Benini (Univ. of Bologna, Italy), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 242 - 247
Detailed information (abstract, keywords, etc)

3A-3 (Time: 16:45 - 17:10)

Title	An Application-centered Design Flow for Self Reconfigurable Systems Implementation
Author	*Fabio Cancare, Marco Domenico Santambrogio, Donatella Sciuto (Politecnico di Milano, Italy)
Page	pp. 248 - 253
Detailed information (abstract, keywords, etc)
Slides

3A-4 (Time: 17:10 - 17:35)

Title	System-Level Process Variability Compensation on Memory Organizations. On the Scalability of Multi-Mode Memories
Author	*Concepción Sanz, Manuel Prieto, José Ignacio Gómez (Univ. Complutense de Madrid, Spain), Antonis Papanikolaou, Francky Catthoor (Inter-Univ. Microelectronics Center, Belgium)
Page	pp. 254 - 259
Detailed information (abstract, keywords, etc)
Slides

Session 3B Advances in Timing Analysis and Modeling
Time: 15:55 - 18:00 Tuesday, January 20, 2009
Location: Room 413
Chairs: Shih-Hsu Huang (Chung Yuan Christian Univ., Taiwan), Atsushi Takahashi (Tokyo Inst. of Tech., Japan)

3B-1 (Time: 15:55 - 16:20)

Title	Accelerating Statistical Static Timing Analysis Using Graphics Processing Units
Author	Kanupriya Gulati, *Sunil P. Khatri (Texas A&M Univ., United States)
Page	pp. 260 - 265
Detailed information (abstract, keywords, etc)
Slides

3B-2 (Time: 16:20 - 16:45)

Title	Trade-off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
Author	*Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ., Japan)
Page	pp. 266 - 271
Detailed information (abstract, keywords, etc)
Slides

3B-3 (Time: 16:45 - 17:10)

Title	Statistical Analysis of On-Chip Power Grid Networks by Variational Extended Truncated Balanced Realization Method
Author	*Duo Li, Sheldon Tan (Univ. of California, Riverside, United States), Gengsheng Chen, Xuan Zeng (Fudan Univ., China)
Page	pp. 272 - 277
Detailed information (abstract, keywords, etc)

3B-4 (Time: 17:10 - 17:35)

Title	Bound-Based Identification of Timing-Violating Paths Under Variability
Author	*Lin Xie, Azadeh Davoodi (Univ. of Wisconsin at Madison, United States)
Page	pp. 278 - 283
Detailed information (abstract, keywords, etc)
Slides

3B-5 (Time: 17:35 - 18:00)

Title	Adaptive Techniques for Overcoming Performance Degradation due to Aging in Digital Circuits
Author	Sanjay Kumar, Chris Kim, *Sachin S. Sapatnekar (Univ. of Minnesota, United States)
Page	pp. 284 - 289
Detailed information (abstract, keywords, etc)
Slides

Session 3D Special Session: Hardware Dependent Software for Multi- and Many-Core Embedded Systems
Time: 15:55 - 18:00 Tuesday, January 20, 2009
Location: Room 416+417
Organizers: Rainer Doemer (Univ. of California, Irvine, United States), Andreas Gerstlauer (Univ. of Texas, Austin, United States), Wolfgang Mueller (Univ. of Paderborn, Germany)

3D-1 (Time: 15:55 - 16:10)

Title	(Invited Paper) Introduction to Hardware-dependent Software Design
Author	*Rainer Dömer (Univ. of California, Irvine, United States), Andreas Gerstlauer (Univ. of Texas, Austin, United States), Wolfgang Müller (Univ. of Paderborn, Germany)
Page	pp. 290 - 292
Detailed information (abstract, keywords, etc)
Slides

3D-2 (Time: 16:10 - 16:50)

Title	(Invited Paper) Using a Dataflow abstracted Virtual Prototype for HdS-Design
Author	Wolfgang Ecker, Stefan Heinen, *Michael Velten (Infineon Technologies AG, Germany)
Page	pp. 293 - 300
Detailed information (abstract, keywords, etc)
Slides

3D-3 (Time: 16:50 - 17:20)

Title	(Invited Paper) Needs and Trends in Embedded Software Development for Consumer Electronics
Author	*Yasutaka Tsunakawa (Sony Corp., Japan)
Page	pp. 301 - 303
Detailed information (abstract, keywords, etc)
Slides

3D-4 (Time: 17:20 - 18:00)

Title	(Invited Paper) Hardware-dependent Software Synthesis for Many-Core Embedded Systems
Author	*Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski (Univ. of California, Irvine, United States)
Page	pp. 304 - 310
Detailed information (abstract, keywords, etc)
Slides

Wednesday, January 21, 2009

Session 2K Keynote Session II
Time: 9:00 - 10:00 Wednesday, January 21, 2009
Location: Small Auditorium, 5F
Chair: Kazutoshi Wakabayashi (NEC Corp., Japan)

2K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) Automated Synthesis and Verification of Embedded Systems: Wishful Thinking or Reality?
Author	Wolfgang Rosenstiel (Wilhelm-Schickard-Institute for Informatics, Univ. of Tuebingen, Germany)
Detailed information (abstract, keywords, etc)

Session 4A System Level Architectures
Time: 10:15 - 12:20 Wednesday, January 21, 2009
Location: Room 411+412
Chairs: Samar Abdi (Univ. of California, Irvine, United States), Jun Yang (Univ. of Pittsburgh)

4A-1 (Time: 10:15 - 10:40)

Title	Computation and Data Transfer Co-Scheduling for Interconnection Bus Minimization
Author	Cathy Qun Xu (Univ. of Texas, Dallas, United States), *Chun Jason Xue, Bessie C Hu (City Univ. of Hong Kong, Hong Kong), Edwin H.M. Sha (Univ. of Texas, Dallas, United States)
Page	pp. 311 - 316
Detailed information (abstract, keywords, etc)

4A-2 (Time: 10:40 - 11:05)

Title	Prototyping Pipelined Applications on a Heterogeneous FPGA Multiprocessor Virtual Platform
Author	*Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani (Politecnico di Milano, Italy), Matteo Monchiero (HP Labs, United States), Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto (Politecnico di Milano, Italy)
Page	pp. 317 - 322
Detailed information (abstract, keywords, etc)
Slides

4A-3 (Time: 11:05 - 11:30)

Title	Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures
Author	*Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria (Politecnico di Milano, DEI, Italy)
Page	pp. 323 - 328
Detailed information (abstract, keywords, etc)
Slides

4A-4 (Time: 11:30 - 11:55)

Title	Partial Conflict-Relieving Programmable Address Shuffler for Parallel Memories in Multi-Core Processor
Author	*Young-Su Kwon, Bon-Tae Koo, Nak-Woong Eum (ETRI, Republic of Korea)
Page	pp. 329 - 334
Detailed information (abstract, keywords, etc)

4A-5 (Time: 11:55 - 12:20)

Title	HitME: Low Power Hit MEmory Buffer for Embedded Systems
Author	Andhi Janapsatya, *Sri Parameswaran, Aleksandar Ignjatovic (Univ. of New South Wales, Australia)
Page	pp. 335 - 340
Detailed information (abstract, keywords, etc)

Session 4B Beyond Traditional Floorplanning and Placement
Time: 10:15 - 12:20 Wednesday, January 21, 2009
Location: Room 413
Chair: Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)

4B-1 (Time: 10:15 - 10:40)

Title	Signal Skew Aware Floorplanning and Bumper Signal Assignment Technique for Flip-Chip
Author	*Cheng-Yu Wang, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 341 - 346
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:40 - 11:05)

Title	A Novel Thermal Optimization Flow Using Incremental Floorplanning for 3D ICs
Author	Xin Li, *Yuchun Ma, Xianlong Hong (Tsinghua Univ., China)
Page	pp. 347 - 352
Detailed information (abstract, keywords, etc)

4B-3 (Time: 11:05 - 11:30)

Title	Analog Placement with Common Centroid and 1-D Symmetry Constraints
Author	*Linfu Xiao, Evangeline Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 353 - 360
Detailed information (abstract, keywords, etc)

4B-4 (Time: 11:30 - 11:55)

Title	A Multilevel Analytical Placement for 3D ICs
Author	Jason Cong, *Guojie Luo (Univ. of California, Los Angeles, United States)
Page	pp. 361 - 366
Detailed information (abstract, keywords, etc)
Slides

4B-5 (Time: 11:55 - 12:20)

Title	Exploring Adjacency in Floorplanning
Author	Jia Wang, *Hai Zhou (Northwestern Univ., United States)
Page	pp. 367 - 372
Detailed information (abstract, keywords, etc)

Session 4C Signal/Power Integrity and Simulation
Time: 10:15 - 12:20 Wednesday, January 21, 2009
Location: Room 414+415
Chairs: Hideki Asai (Shizuoka Univ., Japan), Sheldon Tan (Univ. of California, Riverside, United States)

4C-1 (Time: 10:15 - 10:40)

Title	Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction
Author	*Yiyu Shi (Univ. of California, Los Angeles, United States), Jinjun Xiong, Howard Chen (IBM, United States), Lei He (Univ. of California, Los Angeles, United States)
Page	pp. 373 - 378
Detailed information (abstract, keywords, etc)

4C-2 (Time: 10:40 - 11:05)

Title	Fast Analysis of Nontree-Clock Network Considering Environmental Uncertainty by Parameterized and Incremental Macromodeling
Author	Hai Wang (Univ. of California, Riverside, United States), Hao Yu (Berkeley Design Automation, United States), *Sheldon X.D. Tan (Univ. of California, Riverside, United States)
Page	pp. 379 - 384
Detailed information (abstract, keywords, etc)

4C-3 (Time: 11:05 - 11:30)

Title	High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication
Author	Ling Zhang, Yulei Zhang (Univ. of California, San Diego, United States), Akira Tsuchiya (Kyoto Univ., Japan), Masanori Hashimoto (Osaka Univ., Japan), Ernest Kuh (Univ. of California, Berkeley, United States), *Chung-Kuan Cheng (Univ. of California, San Diego, United States)
Page	pp. 385 - 390
Detailed information (abstract, keywords, etc)

4C-4 (Time: 11:30 - 11:55)

Title	Noise Minimization During Power-Up Stage for a Multi-Domain Power Network
Author	*Wanping Zhang (Qualcomm Inc./Univ. of California, San Diego, United States), Yi Zhu (Univ. of California, San Diego, United States), Wenjian Yu (Tsinghua Univ., China), Amirali Shayan, Renshen Wang (Univ. of California, San Diego, United States), Zhi Zhu (Qualcomm Inc., United States), Chung-Kuan Cheng (Univ. of California, San Diego, United States)
Page	pp. 391 - 396
Detailed information (abstract, keywords, etc)

4C-5s (Time: 11:55 - 12:07)

Title	Parallel Transistor Level Circuit Simulation using Domain Decomposition Methods
Author	*He Peng, Chung-Kuan Cheng (Univ. of California, San Diego, United States)
Page	pp. 397 - 402
Detailed information (abstract, keywords, etc)

4C-6s (Time: 12:07 - 12:19)

Title	Fast Circuit Simulation on Graphics Processing Units
Author	Kanupriya Gulati (Texas A&M Univ., United States), John F. Croix (Nascentric, Inc., United States), *Sunil P. Khatri (Texas A&M Univ., United States), Rahm Shastry (Nascentric, Inc., United States)
Page	pp. 403 - 408
Detailed information (abstract, keywords, etc)
Slides

Session 4D Special Session: Challenges in 3D Integrated Circuit Design
Time: 10:15 - 12:20 Wednesday, January 21, 2009
Location: Room 416+417
Organizer: Sachin Sapatnekar (Univ. of Minnesota, United States)

4D-1 (Time: 10:15 - 10:40)

Title	(Invited Paper) Three-Dimensional Integration Technology and Integrated Systems
Author	*Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka (Tohoku Univ., Japan)
Page	pp. 409 - 415
Detailed information (abstract, keywords, etc)
Slides

4D-2 (Time: 10:40 - 11:05)

Title	(Invited Paper) A 3D Prototyping Chip based on a Wafer-level Stacking Technology
Author	*Nobuaki Miyakawa (Honda Research Institute, Japan)
Page	pp. 416 - 420
Detailed information (abstract, keywords, etc)

4D-3 (Time: 11:05 - 11:30)

Title	(Invited Paper) CAD Challenges for 3D ICs
Author	David Kung, *Ruchir Puri (IBM Corp., United States)
Page	pp. 421 - 422
Detailed information (abstract, keywords, etc)

4D-4 (Time: 11:30 - 11:55)

Title	(Invited Paper) Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits
Author	*Sachin S. Sapatnekar (Univ. of Minnesota, United States)
Page	pp. 423 - 428
Detailed information (abstract, keywords, etc)
Slides

4D-5 (Time: 11:55 - 12:20)

Title	(Invited Paper) The Road to 3D EDA Tool Readiness
Author	*Charles Chiang, Subarna Sinha (Synopsys, United States)
Page	pp. 429 - 436
Detailed information (abstract, keywords, etc)

Session 5A Energy-Aware System Level Design Methodology
Time: 13:30 - 15:35 Wednesday, January 21, 2009
Location: Room 411+412
Chairs: Chia-Lin Yang (National Taiwan Univ., Taiwan), Juinn-Dar Huang (National Chiao Tung Univ.)

5A-2 (Time: 13:55 - 14:20)

Title	System-Level Exploration Tool for Energy-Aware Memory Management in the Design of Multidimensional Signal Processing Systems
Author	*Florin Balasa (Southern Utah Univ., United States), Ilie I. Luican (Univ. of Illinois, Chicago, United States), Hongwei Zhu (ARM, Inc., United States), Doru V. Nasui (American International Radio, Inc., United States)
Page	pp. 443 - 448
Detailed information (abstract, keywords, etc)

5A-3 (Time: 14:20 - 14:45)

Title	Systematic Architecture Exploration based on Optimistic Cycle Estimation for Low Energy Embedded Processors
Author	*Ittetsu Taniguchi (Osaka Univ., Japan), Murali Jayapala (IMEC vzw., Belgium), Praveen Raghavan, Francky Catthoor (IMEC vzw./K.U.Leuven, Belgium), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 449 - 454
Detailed information (abstract, keywords, etc)
Slides

5A-4 (Time: 14:45 - 15:10)

Title	A Framework for Estimating NBTI Degradation of Microarchitectural Components
Author	*Michael DeBole, Ramakrishnan Krishnan (Pennsylvania State Univ., United States), Varsha Balakrishnan, Wenping Wang (Arizona State Univ., United States), Hong Luo, Yu Wang (Tsinghua Univ., China), Yuan Xie (Pennsylvania State Univ., United States), Yu Cao (Arizona State Univ., United States), N. Vijaykrishnan (Pennsylvania State Univ., United States)
Page	pp. 455 - 460
Detailed information (abstract, keywords, etc)

Session 5B Design for Manufacturing and Reliability
Time: 13:30 - 15:35 Wednesday, January 21, 2009
Location: Room 413
Chair: Charles Chiang (Synopsys, United States)

5B-1 (Time: 13:30 - 13:55)

Title	Efficient Analytical Determination of the SEU-induced Pulse Shape
Author	Rajesh Garg, *Sunil P. Khatri (Texas A&M Univ., United States)
Page	pp. 461 - 467
Detailed information (abstract, keywords, etc)

5B-2 (Time: 13:55 - 14:20)

Title	Post-Routing Redundant Via Insertion with Wire Spreading Capability
Author	Cheok-Kei Lei, *Po-Yi Chiang, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Page	pp. 468 - 473
Detailed information (abstract, keywords, etc)

5B-3 (Time: 14:20 - 14:45)

Title	Accounting for Non-linear Dependence Using Function Driven Component Analysis
Author	Lerong Cheng, *Puneet Gupta, Lei He (Univ. of California, Los Angeles, United States)
Page	pp. 474 - 479
Detailed information (abstract, keywords, etc)

5B-4 (Time: 14:45 - 15:10)

Title	Risk Aversion Min-Period Retiming under Process Variations
Author	Jia Wang, *Hai Zhou (Northwestern Univ., United States)
Page	pp. 480 - 485
Detailed information (abstract, keywords, etc)

5B-5s (Time: 15:10 - 15:22)

Title	Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography
Author	Kwangok Jeong, *Andrew B. Kahng (Univ. of California, San Diego, United States)
Page	pp. 486 - 491
Detailed information (abstract, keywords, etc)

5B-6s (Time: 15:22 - 15:34)

Title	Scheduled Voltage Scaling for Increasing Lifetime in the Presence of NBTI
Author	*Lide Zhang, Robert Dick (Northwestern Univ., United States)
Page	pp. 492 - 497
Detailed information (abstract, keywords, etc)

Session 5C Analog, RF and Mixed-Signal CAD
Time: 13:30 - 15:35 Wednesday, January 21, 2009
Location: Room 414+415
Chairs: Eric Keiter (Sandia National Laboratories, United States), Chin-Fong Chiu (National Chip Implementation Center, Taiwan)

5C-1 (Time: 13:30 - 13:55)

Title	Efficiently Finding the 'Best' Solution with Multi-Objectives from Multiple Topologies in Topology Library of Analog Circuit
Author	*Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya (Fujitsu Laboratories Ltd., Japan)
Page	pp. 498 - 503
Detailed information (abstract, keywords, etc)
Slides

5C-2 (Time: 13:55 - 14:20)

Title	Automated Design and Optimization of Circuits in Emerging Technologies
Author	*Rajesh A. Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil (IIT Bombay, India)
Page	pp. 504 - 509
Detailed information (abstract, keywords, etc)

5C-3 (Time: 14:20 - 14:45)

Title	An Automated Design Approach for CMOS LDO Regulators
Author	*Samiran DasGupta, Pradip Mandal (IIT Kharagpur, India)
Page	pp. 510 - 515
Detailed information (abstract, keywords, etc)

5C-4 (Time: 14:45 - 15:10)

Title	A SCORE Macromodel for PLL Designs to Analyze Supply Noise Interaction Issues at Behavioral Level
Author	*Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu (National Central Univ., Taiwan)
Page	pp. 516 - 521
Detailed information (abstract, keywords, etc)

5C-5 (Time: 15:10 - 15:35)

Title	Gen-Adler: The Generalized Adler’s Equation for Injection Locking Analysis in Oscillators
Author	*Prateek Bhansali, Jaijeet Roychowdhury (Univ. of Minnesota, United States)
Page	pp. 522 - 527
Detailed information (abstract, keywords, etc)
Slides

Session 5D Designers' Forum: Consumer SoC
Time: 13:30 - 15:35 Wednesday, January 21, 2009
Location: Room 416+417
Chair: Yoshio Masubuchi (Toshiba Corp., Japan)

5D-1 (Time: 13:30 - 14:10)

Title	(Invited Paper) Development of Full-HD Multi-standard Video CODEC IP Based on Heterogeneous Multiprocessor Architecture
Author	*Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira (Hitachi, Ltd., Japan), Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori (Renesas Technology Corp., Japan)
Page	pp. 528 - 534
Detailed information (abstract, keywords, etc)
Slides

5D-2 (Time: 14:10 - 14:50)

Title	(Invited Paper) A 65nm Dual-mode Baseband and Multimedia Application Processor SoC with Advanced Power and Memory Management
Author	*Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka (Renesas Technology Corp., Japan)
Page	pp. 535 - 539
Detailed information (abstract, keywords, etc)
Slides

5D-3 (Time: 14:50 - 15:30)

Title	(Invited Paper) UniPhier: Series Development and SoC Management
Author	*Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji Horii, Hisato Yoshida (Panasonic Corp., Japan)
Page	pp. 540 - 545
Detailed information (abstract, keywords, etc)

Session 6A System Level Simulation and Modeling
Time: 15:55 - 18:00 Wednesday, January 21, 2009
Location: Room 411+412
Chairs: Vincent J Mooney (Georgia Inst. of Tech., United States), Tsuneo Nakata (Fujitsu Laboratories Ltd., Japan)

6A-1 (Time: 15:55 - 16:20)

Title	Automatic Instrumentation of Embedded Software for High Level Hardware/Software Co-Simulation
Author	Aimen Bouchhima, *Patrice Gerin, Frédéric Pétrot (TIMA Lab., France)
Page	pp. 546 - 551
Detailed information (abstract, keywords, etc)
Slides

6A-2 (Time: 16:20 - 16:45)

Title	Fast and Accurate Performance Simulation of Embedded Software for MPSoC
Author	*Eric Cheung, Harry Hsieh (Univ. of California, Riverside, United States), Felice Balarin (Cadence Design Systems, United States)
Page	pp. 552 - 557
Detailed information (abstract, keywords, etc)

6A-3 (Time: 16:45 - 17:10)

Title	Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model
Author	*Chen Kang Lo, Ren Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 558 - 563
Detailed information (abstract, keywords, etc)
Slides

6A-4 (Time: 17:10 - 17:35)

Title	A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor
Author	*Farhad Mehdipour (Kyushu Univ., Japan), Hamid Noori (ISIT, Japan), Bahman Javadi (Amirkabir Univ. of Tech., Iran), Hiroaki Honda (ISIT, Japan), Koji Inoue, Kazuaki Murakami (Kyushu Univ., Japan)
Page	pp. 564 - 569
Detailed information (abstract, keywords, etc)
Slides

Session 6B Chip and Package Routing Techniques
Time: 15:55 - 18:00 Wednesday, January 21, 2009
Location: Room 413
Chairs: Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

6B-1 (Time: 15:55 - 16:20)

Title	Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
Author	Ke-Ren Dai, *Wen-Hao Liu, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 570 - 575
Detailed information (abstract, keywords, etc)

6B-2 (Time: 16:20 - 16:45)

Title	FastRoute 4.0: Global Router with Efficient Via Minimization
Author	*Yue Xu, Yanheng Zhang, Chris Chu (Iowa State Univ., United States)
Page	pp. 576 - 581
Detailed information (abstract, keywords, etc)

6B-3s (Time: 16:45 - 16:57)

Title	High-Performance Global Routing with Fast Overflow Reduction
Author	*Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 582 - 587
Detailed information (abstract, keywords, etc)

6B-4s (Time: 16:57 - 17:09)

Title	IO Connection Assignment and RDL Routing for Flip-Chip Designs
Author	Jin-Tai Yan, *Zhi-Wei Chen (Chung Hua Univ., Taiwan)
Page	pp. 588 - 593
Detailed information (abstract, keywords, etc)

6B-5 (Time: 17:09 - 17:34)

Title	On Using SAT to Ordered Escape Problems
Author	Lijuan Luo, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 594 - 599
Detailed information (abstract, keywords, etc)

6B-6 (Time: 17:34 - 17:59)

Title	A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound
Author	*Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 600 - 605
Detailed information (abstract, keywords, etc)

Session 6D Designers' Forum: ESL Design Methods
Time: 15:55 - 18:00 Wednesday, January 21, 2009
Location: Room 416+417

6D-1

Title	(Panel Discussion) ESL Design Methods
Author	Moderator: Takashi Hasegawa (Fujitsu Microelectronics Ltd., Japan), Panelists: Simon Bloch (Mentor Graphics Corp., United States), Ahmed Jerraya (CEA-LETI, France), Gabriela Nicolescu (Ecole Polytechnique de Montreal, Canada), Shigeru Oho (Hitachi, Ltd., Japan), Koichiro Yamashita (Fujitsu Labs. Ltd., Japan)
Detailed information (abstract, keywords, etc)

Thursday, January 22, 2009

Session 3K Keynote Session III
Time: 9:00 - 10:00 Thursday, January 22, 2009
Location: Small Auditorium, 5F
Chair: Kazutoshi Wakabayashi (NEC Corp., Japan)

3K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) From Restrictive to Prescriptive Design
Author	Leon Stok (IBM, United States)
Detailed information (abstract, keywords, etc)

Session 7A Compilation Techniques for Embedded Systems
Time: 10:15 - 12:20 Thursday, January 22, 2009
Location: Room 411+412
Chairs: Hiroyuki Tomiyama (Nagoya Univ., Japan), Maziar Goudarzi (Kyushu Univ., Japan)

7A-1 (Time: 10:15 - 10:40)

Title	Thermal-aware Post Compilation for VLIW Architectures
Author	*Wen-Wen Hsieh, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Page	pp. 606 - 611
Detailed information (abstract, keywords, etc)
Slides

7A-2 (Time: 10:40 - 11:05)

Title	A Software Solution for Dynamic Stack Management on Scratch Pad Memory
Author	Arun Kannan, *Aviral Shrivastava, Amit Pabalkar, Jong-eun Lee (Arizona State Univ., United States)
Page	pp. 612 - 617
Detailed information (abstract, keywords, etc)

7A-3 (Time: 11:05 - 11:30)

Title	Compiler-Managed Register File Protection for Energy-Efficient Soft Error Reduction
Author	Jongeun Lee, *Aviral Shrivastava (Arizona State Univ., United States)
Page	pp. 618 - 623
Detailed information (abstract, keywords, etc)

7A-4 (Time: 11:30 - 11:55)

Title	Code Decomposition and Recomposition for Enhancing Embedded Software Performance
Author	*Youngchul Cho (SAIT, Samsung Electoronics, Republic of Korea), Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 624 - 629
Detailed information (abstract, keywords, etc)

Session 7B Sequential Design Verification
Time: 10:15 - 12:20 Thursday, January 22, 2009
Location: Room 413
Chairs: Yosinori Watanabe (Cadence, United States), Chung-Yang Huang (National Taiwan Univ., Taiwan)

7B-1 (Time: 10:15 - 10:40)

Title	Dependent Latch Identification in the Reachable State Space
Author	Chen-Hsuan Lin, *Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 630 - 635
Detailed information (abstract, keywords, etc)

7B-2 (Time: 10:40 - 11:05)

Title	Complete-k-Distinguishability for Retiming and Resynthesis Equivalence Checking without Restricting Synthesis
Author	Nikolaos Liveris, *Hai Zhou (Northwestern Univ., United States), Prithviraj Banerjee (HP Labs, United States)
Page	pp. 636 - 641
Detailed information (abstract, keywords, etc)

7B-4 (Time: 11:30 - 11:55)

Title	Multi-Clock SVA Synthesis without Re-writing
Author	*Jiang Long, Andrew Seawright, Paparao Kavalipati (Mentor Graphics Corp., United States)
Page	pp. 648 - 653
Detailed information (abstract, keywords, etc)

7B-5 (Time: 11:55 - 12:20)

Title	Automatic Formal Verification of Clock Domain Crossing Signals
Author	*Bing Li, Chris Ka-Kei Kwok (Mentor Graphics Corp., United States)
Page	pp. 654 - 659
Detailed information (abstract, keywords, etc)
Slides

Session 7C Scan Test Generation
Time: 10:15 - 12:20 Thursday, January 22, 2009
Location: Room 414+415
Chair: Satoshi Ohtake (NAIST, Japan)

7C-1 (Time: 10:15 - 10:40)

Title	Fast False Path Identification Based on Functional Unsensitizability Using RTL Information
Author	*Yuki Yoshikawa (Hiroshima City Univ., Japan), Satoshi Ohtake (NAIST, Japan), Tomoo Inoue (Hiroshima City Univ., Japan), Hideo Fujiwara (NAIST, Japan)
Page	pp. 660 - 665
Detailed information (abstract, keywords, etc)
Slides

7C-2 (Time: 10:40 - 11:05)

Title	Conflict Driven Scan Chain Configuration for High Transition Fault Coverage and Low Test Power
Author	*Zhen Chen, Boxue Yin, Dong Xiang (Tsinghua Univ., China)
Page	pp. 666 - 671
Detailed information (abstract, keywords, etc)
Slides

7C-3 (Time: 11:05 - 11:30)

Title	Dynamic Test Compaction for a Random Test Generation Procedure with Input Cube Avoidance
Author	Irith Pomeranz (Purdue Univ., United States), *Sudhakar Reddy (Univ. of Iowa, United States)
Page	pp. 672 - 677
Detailed information (abstract, keywords, etc)

7C-4 (Time: 11:30 - 11:55)

Title	Detectability of Internal Bridging Faults in Scan Chains
Author	*Fan Yang (Univ. of Iowa, United States), Sreejit Chakravarty, Narendra Devta-Prasanna (LSI Corp., United States), Sudhakar M. Reddy (Univ. of Iowa, United States), Irith Pomeranz (Purdue Univ., United States)
Page	pp. 678 - 683
Detailed information (abstract, keywords, etc)

7C-5 (Time: 11:55 - 12:20)

Title	Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
Author	*Bing-Chuan Bai (National Taiwan Univ., Taiwan), Augusli Kifli (Faraday Technology Corp., Taiwan), Chien-Mo Li (National Taiwan Univ., Taiwan), Kun-Cheng Wu (Faraday Technology Corp., Taiwan)
Page	pp. 684 - 689
Detailed information (abstract, keywords, etc)

Session 7D Designers' Forum: Analog/RF Circuit Designs
Time: 10:15 - 12:20 Thursday, January 22, 2009
Location: Room 416+417
Chair: Makoto Ikeda (Univ. of Tokyo, Japan)

7D-1 (Time: 10:15 - 10:45)

Title	(Invited Paper) Design Methods for Pipeline & Delta-Sigma A-to-D Converters with Convex Optimization
Author	*Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho (Panasonic Corp., Japan)
Page	pp. 690 - 695
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7D-2 (Time: 10:45 - 11:15)

Title	(Invited Paper) A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA
Author	*Takashi Kawamoto, Masaru Kokubo (Hitachi, Ltd., Japan)
Page	pp. 696 - 701
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7D-3 (Time: 11:15 - 11:45)

Title	(Invited Paper) RF-Analog Circuit Design in Scaled SoC
Author	*Nobuyuki Itoh, Mototsugu Hamada (Toshiba Corp., Japan)
Page	pp. 702 - 707
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7D-4 (Time: 11:45 - 12:15)

Title	(Invited Paper) An Approach to the RF-LSI Design for Ubiquitous Communication Appliances
Author	*Yuichi Kado, Mitsuru Harada (NTT, Japan)
Page	pp. 708 - 714
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Session 8A High-Level Design and Scheduling
Time: 13:30 - 15:35 Thursday, January 22, 2009
Location: Room 411+412
Chairs: Yuichi Nakamura (NEC Corp., Japan), Keishi Sakanushi (Osaka Univ., Japan)

8A-1 (Time: 13:30 - 13:55)

Title	Improving Scalability of Model-Checking for Minimizing Buffer Requirements of Synchronous Dataflow Graphs
Author	Nan Guan (Northeastern Univ., China), *Zonghua Gu (HKUST, China), Wang Yi (Uppsala Univ., Sweden), Ge Yu (Northeastern Univ., China)
Page	pp. 715 - 720
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Slides

8A-2 (Time: 13:55 - 14:20)

Title	A Reverse-Encoding-based on-chip AHB Bus Tracer for Efficient Circular Buffer Utilization
Author	*Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 721 - 726
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Slides

8A-3 (Time: 14:20 - 14:45)

Title	Analyzing and Optimizing Energy Efficiency of Algorithms on DVS Systems: a First Step towards Algorithmic Energy Minimization
Author	*Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ., Japan)
Page	pp. 727 - 732
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Slides

8A-4 (Time: 14:45 - 15:10)

Title	Novel Task Migration Framework on Configurable Heterogeneous MPSoC Platforms
Author	Hao Shen, *Frédéric Pétrot (TIMA Lab., France)
Page	pp. 733 - 738
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Slides

Session 8B Emerging Design Methodologies and Applications
Time: 13:30 - 15:35 Thursday, January 22, 2009
Location: Room 413
Chair: Chin-Long Wey (National Central Univ., Taiwan)

8B-1 (Time: 13:30 - 13:55)

Title	A Novel Toffoli Network Synthesis Algorithm for Reversible Logic
Author	*Yexin Zheng, Chao Huang (Virginia Tech, United States)
Page	pp. 739 - 744
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8B-2 (Time: 13:55 - 14:20)

Title	A Cycle-Based Synthesis Algorithm for Reversible Logic
Author	*Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani (Amirkabir Univ. of Tech., Iran)
Page	pp. 745 - 750
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Slides

8B-3 (Time: 14:20 - 14:45)

Title	Array Like Runtime Reconfigurable MIMO Detectors for 802.11n WLAN: A Design Case Study
Author	Pankaj Bhagawat, Rajballav Dash, *Gwan Choi (Texas A&M Univ., United States)
Page	pp. 751 - 756
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8B-4 (Time: 14:45 - 15:10)

Title	Mapping method for Dynamically Reconfigurable Architecture
Author	*Akira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano (Toshiba Corp., Japan)
Page	pp. 757 - 762
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8B-5 (Time: 15:10 - 15:35)

Title	A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner
Author	Srinath Sridharan, *Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan (Pennsylvania State Univ., United States)
Page	pp. 763 - 768
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Session 8C Verification, Test, and Yield
Time: 13:30 - 15:35 Thursday, January 22, 2009
Location: Room 414+415
Chairs: Yasuo Sato (Hitachi, Ltd., Japan), Sudhakar M. Reddy (Univ. of Iowa, United States)

8C-1 (Time: 13:30 - 13:55)

Title	Self-Adjusting Constrained Random Stimulus Generation Using Splitting Evenness Evaluation and XOR Constraints
Author	Shujun Deng, Zhiqiu Kong, *Jinian Bian, Yanni Zhao (Tsinghua Univ., China)
Page	pp. 769 - 774
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Slides

8C-2 (Time: 13:55 - 14:20)

Title	Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input
Author	*Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang (National Taiwan Univ., Taiwan)
Page	pp. 775 - 780
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8C-3 (Time: 14:20 - 14:45)

Title	Path Selection for Monitoring Unexpected Systematic Timing Effects
Author	*Nicholas Callegari, Pouria Bastani, Li-C. Wang (Univ. of California, Santa Barbara, United States), Sreejit Chakravarty, Alexander Tetelbaum (LSI Corp., United States)
Page	pp. 781 - 786
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Slides

8C-4 (Time: 14:45 - 15:10)

Title	Design for Burn-In Test: A Technique for Burn-In Thermal Stability under Die-to-Die Parameter Variations
Author	Mesut Meterelliyoz, *Kaushik Roy (Purdue Univ., United States)
Page	pp. 787 - 792
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8C-5 (Time: 15:10 - 15:35)

Title	Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints
Author	*Thomas Edison Yu, Tomokazu Yoneda (NAIST, Japan), Krishnendu Chakrabarty (Duke Univ., United States), Hideo Fujiwara (NAIST, Japan)
Page	pp. 793 - 798
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Slides

Session 8D Designers' Forum: Near-Future SoC Architectures -- Can Dynamically Reconfigurable Processors be a Key Technology?
Time: 13:30 - 15:35 Thursday, January 22, 2009
Location: Room 416+417

8D-1

Title	(Panel Discussion) Near-Future SoC Architectures -- Can Dynamically Reconfigurable Processors be a Key Technology?
Author	Moderator: Hideharu Amano (Keio Univ., Japan), Panelists: Toru Awashima (NEC Corp., Japan), Hisanori Fujisawa (Fujitsu Laboratories Ltd., Japan), Naohiko Irie (Hitachi, Ltd., Japan), Takashi Miyamori (Toshiba Corp., Japan), Tony Stansfield (Panasonic Europe Ltd., Great Britain)
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Session 9A Memory Systems Simulation and Optimization
Time: 15:55 - 18:00 Thursday, January 22, 2009
Location: Room 411+412
Chair: Zonghua Gu (HKUST, Hong Kong)

9A-1 (Time: 15:55 - 16:20)

Title	Soft Lists: A Native Index Structure for NOR-Flash-Based Embedded Devices
Author	*Li-Pin Chang, Chen-Hui Hsu (National Chiao Tung Univ., Taiwan)
Page	pp. 799 - 804
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9A-2 (Time: 16:20 - 16:45)

Title	Energy-aware Register File Re-Partitioning for Clustered VLIW Architectures
Author	*Chun Jason Xue, Minming Li, Yingchao Zhao, Bessie Hu (City Univ. of Hong Kong, Hong Kong)
Page	pp. 805 - 810
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9A-3 (Time: 16:45 - 17:10)

Title	Memory Subsystem Simulation in Software TLM/T Models
Author	*Eric Cheung, Harry Hsieh (Univ. of California, Riverside, United States), Felice Balarin (Cadence Design Systems, United States)
Page	pp. 811 - 816
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9A-4 (Time: 17:10 - 17:35)

Title	Exact and Fast L1 Cache Simulation for Embedded Systems
Author	*Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Page	pp. 817 - 822
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9A-5 (Time: 17:35 - 18:00)

Title	Accuracy-Aware SRAM: A Reconfigurable Low Power SRAM Architecture for Mobile Multimedia Applications
Author	Minki Cho (Georgia Inst. of Tech., United States), Jason Schlessman (Princeton Univ., United States), *Wayne Wolf, Saibal Mukhopadhyay (Georgia Inst. of Tech., United States)
Page	pp. 823 - 828
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Session 9B Emerging Technologies
Time: 15:55 - 18:00 Thursday, January 22, 2009
Location: Room 413
Chair: Mehdi Baradaran Tahoori (Northeastern Univ., United States)

9B-1 (Time: 15:55 - 16:20)

Title	High-Speed Low-Power FinFET Based Domino Logic
Author	Seid Hadi Rasouli (Univ. of California, Santa Barbara, United States), Hanpei Koike (AIST, Japan), *Kaustav Banerjee (Univ. of California, Santa Barbara, United States)
Page	pp. 829 - 834
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9B-2 (Time: 16:20 - 16:45)

Title	A Stochastic Perturbative Approach to Design a Defect-Aware Thresholder in the Sense Amplifier of Crossbar Memories
Author	*M. Haykel Ben Jamaa (EPFL, Switzerland), David Atienza (Univ. Complutense de Madrid, Spain), Yusuf Leblebici, Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 835 - 840
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Slides

9B-3 (Time: 16:45 - 17:10)

Title	An Alternate Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) from Circuit/Architecture Perspective
Author	Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, *Kaushik Roy (Purdue Univ., United States)
Page	pp. 841 - 846
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9B-4 (Time: 17:10 - 17:35)

Title	A Design Methodology and Device/Circuit/Architecture Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems
Author	Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, *Kaushik Roy (Purdue Univ., United States)
Page	pp. 847 - 852
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9B-5 (Time: 17:35 - 18:00)

Title	Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture
Author	*Bao Liu (Univ. of Texas, San Antonio, United States)
Page	pp. 853 - 858
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Session 9D Special Session: Dependable VLSI: Device, Design and Architecture -- How should they cooperate ? --
Time: 15:55 - 18:00 Thursday, January 22, 2009
Location: Room 416+417
Organizer: Shuichi Sakai (Univ. of Tokyo, Japan)

9D-1

Title	(Panel Discussion) Dependable VLSI: Device, Design and Architecture -- How should they cooperate ? --
Author	Organizer: Shuichi Sakai (Univ. of Tokyo, Japan), Panelists: Hidetoshi Onodera (Kyoto Univ., Japan), Hiroto Yasuura (Kyushu Univ., Japan), James C. Hoe (Carnegie Mellon Univ., United States)
Page	pp. 859 - 860
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The 14th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of Papers

The 14th Asia and South Pacific Design Automation Conference
Technical Program