Technical Program Committee
Technical Program Chair
Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Technical Program Vice Chair
Shinji Kimura (Waseda Univ., Japan)
Secretary
Jing-Jia Liou (National Tsing Hua Univ., Taiwan)
Sub committees and sub committee chairs
* : subcommittee chairs
- [01] System-Level Design Methodology
- * Ing-Jer Huang (National Sun-Yat-Sen Univ, Taiwan)
- Eui-Young Chung (Yonsei Univ., Korea)
- Xu Cheng (Peking Univ., China)
- Tsuneo Nakata (Fujitsu Lab, Japan)
- Nozomu Togawa (Waseda Univ., Japan)
- Chia-Lin Yang (National Taiwan University, Taiwan)
- Qiang Xu (Chinese University of Hong Kong, Hong Kong)
- Danella Zhao (Univ. of Louisiana at Lafayette, USA)
- [02] System Architecture and Optimization
- * Sri Parameswaran (Univ. of New South Wales, Australia)
- Li Shang (University of Colorado at Boulder, USA)
- Robert Dick (North Western University, USA)
- Karam Chatha (Arizona State Univ., USA)
- Samar Abdi (University of California, Irvine, USA)
- Preeti Ranjan Panda (Indian Institute of Technology, Delhi, India)
- Tulika Mitra (National Univ. of Singapore, Singapore)
- [03] Embedded and Real-Time Systems
- * Samarji Chakraborty (National University of Singapore, Singapore)
- Hiroyuki Tomiyama (Nagoya Univ., Japan)
- Naehyuck Chang (Seoul Nat. Univ., Korea)
- Chi-Sheng Shih (Nat. Taiwan Univ., Taiwan)
- Sungjoo Yoo (Samsung, Korea)
- Pai Chou (UC Irvine, USA)
- Zonghua Gu (HKUST, Hong Kong)
- Paul Pop (Technical University of Denmark, Denmark)
- Gang Quan (University of South Carolina, USA)
- [04] High-Level/Behavioral/Logic Synthesis and Optimization
- * Deming Chen (Univ. of Illinois at Urbana-Champaign, USA)
- Ki-Seok Chung (Hanyang University, Korea)
- Soheil Ghiasi (Univ. of California at Davis, USA)
- Hiroyuki Higuchi (Fujitsu Microelectronics Limited, Japan)
- Taewhan Kim (Seoul National Univ., Korea)
- Yuan Xie (Pennsylvania State Univ., USA)
- Shigeru Yamashita (Nara Institute of Science and Technology, Japan)
- [05] Validation and Verification for Behavioral/Logic Design
- * Shin'ichi Minato (Hokkaido Univ., Japan)
- Chung-Yang Huang (Nat'l Taiwan Univ., Taiwan)
- Igor Markov (Univ. of Michigan, USA)
- Yuichi Nakamura (NEC, Japan)
- Farn Wang (Nat'l Taiwan Univ., Taiwan)
- Yoshinori Watanabe (Cadence, USA)
- [06] Physical Design (Routing)
- * Hyunchul Shin (Hanyang Univ., Korea)
- Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, USA)
- Atsushi Takahashi (Tokyo Inst. Of Tech., Japan)
- Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
- Jeong-Tyng Li (SpringSoft, USA)
- [07] Physical Design (Placement)
- * Wai-Kei Mak (Nat'l Tsing Hua Univ., Taiwan)
- Sherief Reda (Brown University, USA)
- Evangeline F.Y. Young (The Chinese University of Hong Kong, Hong Kong)
- Hung Ming Chen (National Chiao Tung University, Taiwan)
- Gi-Joon Nam (IBM, USA)
- Shigetoshi Nakatake (The University of Kitakyushu, Japan)
- Ameya Agnihotri (Magma, USA)
- [08] Timing, Power, Thermal Analysis and Optimization
- * Youngsoo Shin (KAIST, Korea)
- Matthew Guthaus (Dept. CE, UC Santa Cruz, USA)
- Shabbir Batterywala (Synopsys, India)
- Masanori Hashimoto (Dept. ISE, Osaka University, Japan)
- Shih-Hsu Huang (Chung Yuan Christian Univ, Taiwan)
- Emrah Acar (IBM, USA)
- Farzan Fallah (Fujitsu America, USA)
- [09] Signal/power Integrity, Interconnect/Device/Circuit Modeling and Simulation
- * Hideki Asai (Shizuoka Univ., Japan)
- Takashi Sato (Tokyo Institute of Technology, Japan)
- Yu-Min (Roger) Lee (National Chiao Tung University, Taiwan)
- Yungseon Eo (Hanyang University, Korea)
- Sheldon Tan (University of California Riverside, USA)
- Zuying Luo (Beijing Normal University, China)
- Parthasarathy Ramaswamy (Intel Corporation, India)
- En-Xiao Liu (Institute of High Performance Computing (IHPC), Singapore)
- [10] Design for Manufacturability/Yield and Statistical Design
- * David Pan (The University of Texas at Austin, USA)
- Keh-Jeng Chang (National Tsing Hua University, Taiwan)
- Charles Chiang (Synopsys, USA)
- Puneet Gupta (UCLA, USA)
- Toshiyuki Shibuya (Fujitsu Labs, Japan)
- Hua Xiang (IBM T.J. Watson, USA)
- [11] Test and Design for Testability
- * Seiji Kajihara (Kyushu Institute of Technology, Japan)
- Satoshi Ohtake (NAIST, Japan)
- Shi-Yu Huang (National Tsing-Hua U., Taiwan)
- Wu-Tung Cheng (Menter Graphics, USA)
- Ming-Der Shieh (Cheng-Kung Univ., Taiwan)
- [12] Analog, RF and Mixed Signal Design and CAD
- * Jaijeet Roychowdhury (Univ. of Minnesota, USA)
- Alper Demir (Department of Electrical & Electronics Engineering, Koc University, TURKEY)
- Seongwhan Cho (KAIST, Korea)
- Chin-Fong Chiu (National Chip Implementation Center, Taiwan)
- Tomohisa Kimura (Toshiba Corp., Japan)
- Eric Keiter (Sandia National Labs, Albuquerque, NM, USA)
- [13] Emerging Technologies and Applications
- * Chin-Long Wey (National Central University, Taiwan)
- Shorin Kyo (NEC, Japan)
- In-Cheol Park (Dept of EE, KAIST, Korea)
- Chris Dwyer (Duke University, USA)
- Mehdi Baradaran Tahoori (Electrical & Computer Engineering, Northeastern University, USA)
- Chun-Ming Huang (National Chip Implementation Center, Taiwan)