| Title | Slack Redistribution for Graceful Degradation Under Voltage Overscaling |
| Author | Andrew B. Kahng, *Seokhyeong Kang (UC San Diego, U.S.A.), Rakesh Kumar, John Sartori (UIUC, U.S.A.) |
| Page | pp. 825 - 831 |
| Keyword | power optimization, voltage scaling, slack redistribution, reliability, cell swap |
| Abstract | Modern digital IC designs have a critical operating point,
or “wall of slack”, that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in trading off system reliability and power. We propose a designlevel approach to trading off reliability and voltage (power) in, e.g., microprocessor designs. We increase the range of voltage values at which the (timing) error rate is acceptable; we achieve this through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner. The resulting designs heuristically minimize the voltage at which the maximum allowable error rate is encountered, thus minimizing power consumption for a prescribed maximum error rate and allowing the design to fail more gracefully. Compared with baseline designs, we achieve a maximum of 32.8% and an average of 12.5% power reduction at an error rate of 2%. The area overhead of our techniques, as evaluated through physical implementation (synthesis, placement and routing), is no more than 2.7%. |
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| Title | A Decoder-Based Switch Box to Mitigate Soft Errors in SRAM-Based FPGAs |
| Author | *Hassan Ebrahimi, Morteza Zamani, HamidReza Zarandi (Amirkabir, Iran) |
| Page | pp. 832 - 837 |
| Keyword | Reliability, Soft-error, SRAM-Based FPGAs, Single event upset (SEU), sitch box |
| Abstract | This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated based on several MCNC benchmarks using VPR tool. The experimental results show that this architecture decreases the susceptibility of switch boxes to SEUs about 20% on average compared to the traditional ones. |
| Title | On Process-Aware 1-D Standard Cell Design |
| Author | Hongbo Zhang, *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corporation, U.S.A.) |
| Page | pp. 838 - 842 |
| Keyword | Standard Cell Design, 1-D patterning, Gap Distribution |
| Abstract | When VLSI technology scales down to sub-40nm process node, system process variation introduced by the lithography is a persistent challenge to the manufacturability. The limitation of the resolution enhancement technologies (RETs) forces people to adopt a regular cell design methodology. In this paper, targeted on 1-D cell design, we use simulation data to analyze the relationship between the line-end gap distribution and printability. Based on the gap distribution preferences, an optimal algorithm is provided to efficiently extend the line ends and insert dummies, which will significantly improve the gap distribution and help printability. Experimental results on 45nm and 32nm processes show that significant improvement can be obtained on edge placement error (EPE). |
| Title | D-A Converter Based Variation Analysis for Analog Layout Design |
| Author | *Bo Liu, Toru Fujimura, Bo Yang (University of Kitakyushu, Japan), Shigetoshi Nakatake (University of Kitakyushu, Japan) |
| Page | pp. 843 - 848 |
| Keyword | relative variation, ë-dependency variation, layout structure |
| Abstract | For analog circuits, the current source is one of the most essential functions, and variation of its characteristic seriously influences to the accuracy of the performance. This paper presents a new methodology for analyzing the layout dependency of the variation of the current source transistor. We employ a current-driven D-A converter to investigate the dependency of the current source upon the relative accuracy and the lambda. We implemented the D/A converts with various layout structures into TEG(Test Element Group), and evaluated them. The analysis convinced us that the diffusion sharing and gate folding significantly influence to the variation of lambda and relative accuracy. |
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