| Title | Rule-Based Optimization of Reversible Circuits |
| Author | *Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani (Amirkabir University of Technology, Iran) |
| Page | pp. 849 - 854 |
| Keyword | Reversible circuits, Synthesis, Optimization |
| Abstract | Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed. To evaluate the proposed approach, the best-reported synthesized circuits and the results of a recent synthesis algorithm which uses both negative and positive controls are used. Our experiments reveal the potential of the proposed approach in optimizing synthesized circuits. |
| Slides | |
| Title | Variation Tolerant Logic Mapping for Crossbar Array Nano Architectures |
| Author | Cihan Tunc (Northeastern University, U.S.A.), *Mehdi Tahoori (Northeastern University/Karlsruhe Institute of Technology, U.S.A.) |
| Page | pp. 855 - 860 |
| Keyword | nano crossbar, variation, defect tolerance, logic mapping |
| Abstract | Bottom-up self-assembly nanofabrication process yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. This is in addition to an increased defect density expected for self-assembled nanodevices. Therefore, it is one of the major design challenges to tolerate variation, in addition to defect tolerance, in emerging nano architectures. In this paper, we present a solution for variation tolerant logic mapping for FET based crossbar array nano architectures using Simulated Annealing. Furthermore, we extended the framework for defect tolerance. Experimental results including comparison with exact method confirm the effectiveness of the proposed approach. |
| Slides | |
| Title | Generalised Threshold Gate Synthesis based on AND/OR/NOT Representation of Boolean Function |
| Author | *Marek Arkadiusz Bawiec, Maciej Nikodem (Wrocław University of Technology, Poland) |
| Page | pp. 861 - 866 |
| Keyword | generalised threshold gate, negative differential resistance, boolean logic, synthesis |
| Abstract | This paper focuses on generalized threshold gates (GTGs) that implement boolean logic functions using elements with negative differential resistance (NDR). GTGs are capable of implementing boolean functions, however, no effective synthesis algorithms have been proposed so far. We present that GTGs can be effectively implemented using unate functions. Our synthesis algorithm ensures that the circuit implementing n variable boolean function consists of at most n+2 NDR elements and can be further optimized by reducing the number of switching elements. |
| Slides | |
| Title | Novel Dual-vth Independent-gate FinFET Circuits |
| Author | Masoud Rostami, *Kartik Mohanram (Rice University, U.S.A.) |
| Page | pp. 867 - 872 |
| Keyword | FinFETs, dual-Vth, independent-gate, library |
| Abstract | This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology. |