| Title | Co-Optimization of Memory Access and Task Scheduling on MPSoC Architectures with Multi-Level Memory |
| Author | Yi He (The University of Texas at Dallas, U.S.A.), *Chun Jason Xue (City University of Hong Kong, Hong Kong), Cathy Qun Xu, Edwin Sha (The University of Texas at Dallas, U.S.A.) |
| Page | pp. 95 - 100 |
| Keyword | co-optimization, scheduling, memory access, MPSoC |
| Abstract | An MPSoC system usually consists of a number of processors, a memory hierarchy and a communication mechanism between processors. Because of the gap between the constantly increasing processor speed and slower memory access, how to utilize the memory subsystem more efficiently has become a critical issue for improving the overall system performance. To address this problem, two algorithms are proposed in this paper. The first one uses the integer linear programming method so that the memory access cost is minimized while tasks are scheduled in as short a time as possible. The second one is a heuristic algorithm which can achieve close to optimum results with linear running time. The experimental results show that the memory access cost can be reduced up to 56% comparing to LIST scheduling. |
| Slides | |
| Title | A New Compilation Technique for SIMD Code Generation across Basic Block Boundaries |
| Author | *Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto (Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Japan), Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai (Graduate School of Information Science and Technology, Osaka University, Japan) |
| Page | pp. 101 - 106 |
| Keyword | Compiler Optimization, SIMD instructions, Control Flow |
| Abstract | Although SIMD instructions are effective for many digital signal processing applications, current compilers cannot take full advantage of SIMD instructions. One factor inhibiting SIMD code generation is control flow structure; the target scope of SIMD code generation is currently limited to single basic block or loop that consists of single basic block. SIMD instructions cannot be mapped typically across basic block boundaries even if basic blocks inside the control structure have enough parallelism. In this paper, a new compilation technique to generate SIMD code without modifying control flow structure is proposed. The data dependency between basic blocks is exploited to generate SIMD instructions. The packing cost is introduced for effective vectorization to maintain data dependency across basic block boundaries. Experimental results show that the new SIMD code generation technique reduced 67% of dynamic execution cycles of inter prediction in H.264 decoder. |
| Slides | |
| Title | LibGALS: A Library for GALS Systems Design and Modeling |
| Author | *Wei-Tsun Sun, Zoran Salcic, Avinash Malik (University of Auckland, New Zealand) |
| Page | pp. 107 - 112 |
| Keyword | GALS, Asynchronous, Synchronous, Programming Languages, Operating Systems |
| Abstract | LibGALS is a library and run-time environment that extends a multi-process host operating system (OS) to support the design of Globally Asynchronous Locally Synchronous (GALS) software systems and models. LibGALS provides an application programming interface (API) that enables the designer to describe GALS concurrent programs and reactivity in sequential programming languages. Moreover, it facilitates the interface between the GALS concurrent program and other processes through the services provided by the host OS. LibGALS is also suitable as a target for code generation from GALS and synchronous concurrent languages. The experiments demonstrate code size and run-time gains when compared with other approach to GALS system implementation. |
| Slides | |
| Title | Joint Variable Partitioning and Bank Selection Instruction Optimization on Embedded Systems with Multiple Memory Banks |
| Author | *Tiantian Liu, Minming Li, Chun Jason Xue (City University of Hong Kong, Hong Kong) |
| Page | pp. 113 - 118 |
| Keyword | partitioned memory architecture, bank switching, variable partition |
| Abstract | Bank switching is a technique to increase memory size without extending address buses. A special instruction, Bank Selection Instruction (BSL) is inserted into programs to modify the bank register to point to the right bank, which increases both the code size and runtime overhead. In this paper, we carefully partition variables into different banks and insert BSLs at different positions so that the overheads can be minimized. Minimizing code size and runtime overhead are two objectives investigated in this paper. |
| Slides | |