|Title||(Invited Paper) Design of Networks on Chips for 3D ICs|
|Author||*Srinivasan Murali (iNoCs/EPFL, Switzerland), Luca Benini (University of Bologna, Italy), Giovanni De Micheli (EPFL, Switzerland)|
|Page||pp. 167 - 168|
|Keyword||Networks on Chips, 3D, topology, application-specific|
|Abstract||Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The 3D ICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs.|
|Title||(Panel Discussion) 3D Integration and Networks on Chips (Panel)|
|Author||Organizer & Moderator: Srinivasan Murali (iNoCs/EPFL, Switzerland), Panelists: Ruchir Puri (IBM, U.S.A.), Paull Marchal (IMEC, Belgium), Yuan Xie (Pennsylvania State University, U.S.A.), Ahmed Jerraya (LETI, France), Nobuaki Miyakawa (Honda Research, Japan)|
|Abstract||Vertical stacking of multiple silicon layers, referred to as 3D stacking, is emerging as an attractive solution to continue the pace of growth of Systems on Chips (SoCs). 3D designs have a smaller footprint and shorter wires, leading to lower wire delay and power consumption. Heterogeneous systems can be built effectively, with each layer supporting a diverse technology. The 3D technology has been maturing over the years in addressing thermal issues and achieving high yield.
To tackle the on-chip communication problem, a scalable networking paradigm, Networks on Chips (NoCs) has recently emerged. NoCs provide better structure, modularity and scalability when compared to traditional interconnect solutions.
NoCs are a necessity for 3D chips: they provide arbitrary scalability of the interconnects across additional layers, efficiently parallelize communication in each layer and help controlling the number of vertical wires needed for inter-layer communication. The combined use of 3D integration technologies and NoCs introduces new opportunities and challenges for designers. In this panel, we will discuss the current state-of-the-art of 3D technologies and how NoC based solutions solve the interconnect problems. We will discuss the opportunities and challenges in adopting NoCs for 3D ICs.|