| Title | Three-Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis |
| Author | Paul Falkerstern, Yuan Xie (Pennsylvania State University, U.S.A.), Yao-Wen Chang (National Taiwan University, Taiwan), *Yu Wang (Tsinghua University, China) |
| Page | pp. 169 - 174 |
| Keyword | 3D Integration, Emerging Technology, Floorplanning, Co-design |
| Abstract | Three Dimensional Integrated Circuits (3D ICs) are emerging technology to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools, the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the floorplan and the P/G network concurrently. Most current 3D IC floorplanners neglect the effects of the 3D P/G network on the design, which may lead to large IR drops in the circuit. To create feasible floorplans with efficient P/G networks, the 3D Floorplan and P/G Co-synthesis tool optimizes the floorplan in terms of wirelength, area and P/G routing area and IR drops. The tool integrates a 3D B*-tree floorplan representation, a resistive P/G mesh, and a Simulated Annealing (SA) engine to explore the floorplan and P/G network of a 3D IC. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool show that 3D ICs tend to increase the P/G routing area while decreasing the IR drops in the circuit. By considering the IR drop while floorplanning, exploring the 3D P/G design space, and evaluating 3D IC’s effect on 3D P/G networks, the 3D Floorplan and P/G Co-synthesis tool can develop a more efficient 3D IC. |
| Title | Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) Based 3D ICs |
| Author | *Xin Zhao, Sung Kyu Lim (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 175 - 180 |
| Keyword | 3D clock delivery, low power, clock slew control |
| Abstract | In this paper, three effective design techniques are presented to effectively reduce the clock power consumption and slew of the 3D clock distribution network: (1) controlling the bound of through-silicon-vias (TSVs) used in between adjacent dies, (2) controlling the maximum load capacitance of the clock buffer, (3) adjusting the clock source location in the 3D stack. We discuss how these design factors affect the overall wirelength, clock power, slew, skew, and routing congestion in the practical 3D clock network design. SPICE simulation indicates that: (1) a 3D clock tree with multiple TSVs achieves up to 31% power saving, 52% wirelength saving and better slew control as compared with the single-TSV case; (2) by placing the clock source on the middle die in the 3D stack, an additional 7.7% power savings, 9.2% wirelength savings, and 33% TSV savings are obtained compared with the clock source on the topmost die. This work aims at helping designers construct reliable low-power and low-slew 3D clock network by making the right decisions on TSV usage, clock buffer insertion, and clock source placement. |
| Slides | |
| Title | A Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V VDD Applications |
| Author | Jawar Singh (University of Bristol, U.K.), Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, *Vijaykrishnan Narayanan (The Pennsylvania State University, U.S.A.), Dhiraj Pradhan (University of Bristol, U.K.) |
| Page | pp. 181 - 186 |
| Keyword | TFET, SRAM |
| Abstract | Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si- TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at VDD of 0.3V and 0.5V which makes it suitable for use at ultra-low power applications. |
| Title | CAD Reference Flow for 3D Via-Last Integrated Circuits |
| Author | *Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen-Ching Wu (SoC Technology Center, Industrial Technology Research Institute, Taiwan) |
| Page | pp. 187 - 192 |
| Keyword | 3D-LSI, CAD, Via-last, Through-Silicon Via (TSV), Face-to-Back Bonding |
| Abstract | Next-decade computing power and interconnect bottle-neck challenge conventional IC design due to the ever increasing demands for high frequency and great bandwidth. Three-dimensional large-scale integration (3D-LSI) provides an opportunity to realize such high performance cores while reducing long latency. In this paper, we present a reference flow for the implementation of 3D via-last ICs in scalable face-to-back bonding style which leverages a mature set of 2D IC physical design tools. The first enabling technology of 3D-LSI is through-silicon via (TSV). Two kinds of TSV diameters are exemplified in the flow, namely, 5μm and 50μm. We propose an easy-to-adopt method to address the TSV-aware mixed-sized placement by considering the obstructions generated from adjacent-tier's floorplan, subject to certain TSV alignment constraints. Furthermore, the technique of clock tree synthesis (CTS) for a homogeneous die stack is developed to dramatically reduce the clock latency and skew. The mixed-sized placement and CTS of each tier can be done without iteration. To the best of our knowledge, no work has ever been published in literature discussing CTS for 3D via-last integration in a face-to-back fashion. Finally, to complete the proposed flow 2D timing-driven routing and modified off-line design rule check (DRC) and layout versus schematic (LVS) verification are performed very well. |
| Slides | |
| Title | Energy and Performance Driven Circuit Design for Emerging Phase-Change Memory |
| Author | Dimin Niu, *Yibo Chen, Xiangyu Dong, Yuan Xie (The Pennsylvania State University, U.S.A.) |
| Page | pp. 193 - 198 |
| Keyword | Phase Change Memory, access device, design methodology |
| Abstract | Phase-Change Random Access Memory (PRAM) has become one of the most promising emerging memory technologies, due to its attractive features such as high density, fast access, non-volatility, and good scalability. The physical characteristics of a PRAM cell mainly depend on the material characteristic and the fabrication process. However, the access device and the operating voltage have significant impact on the PRAM performance, energy dissipation, and lifetime. In this paper, we study the design constraints for PRAM memory array, and propose design optimizations of the access device and the circuit operational voltage. The important features of PRAM memory, such as power consumption, read/write stability, speed, as well as lifetime are all considered as the constrained conditions in the proposed optimizations. Experimental results showed that the proposed methodology can provide a reliable design space for the access device and the operating voltage. |