| Title | Current Source Modeling in the Presence of Body Bias |
| Author | Saket Gupta, *Sachin S. Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 199 - 204 |
| Keyword | Current source modeling, timing analysis, body bias |
| Abstract | With the increasing use of adaptive body biases in high-performance
designs, it has become necessary to build timing models that
can include these effects. State-of-the-art timing tools use current source
models (CSMs), which have proven to be fast and accurate. However, a
straightforward extension of CSMs to incorporate multiple body biases
results in unreasonably large characterization tables for each cell. We
propose a new approach to compactly capture body bias effects within a
mainstream CSM framework. Our approach features a table reduction
method for compact storage, and a fast and novel waveform sensitivity
method for timing evaluation. On a 45nm technology, we demonstrate
high accuracy, with worst-case errors of under 5% in both slew and
delay as compared to HSPICE. We show a speedup of over five orders
of magnitude over HSPICE and almost 70x over conventional CSMs. |
| Slides |
| Title | Manifold Construction and Parameterization for Nonlinear Manifold-Based Model Reduction |
| Author | *Chenjie Gu, Jaijeet Roychowdhury (University of California, Berkeley, U.S.A.) |
| Page | pp. 205 - 210 |
| Keyword | Model Reduction, Manifold, Integral Curve |
| Abstract | We present a new manifold construction and parameterization algorithm
for model reduction approaches based on projection on manifolds. The
new algorithm employs two key ideas: (1) we define an ideal manifold
for nonlinear model reduction to be the solution of a set of
differential equations with the property that the tangent space at any
point on the manifold spans the same subspace as the low-order
subspace (e.g., Krylov subspace generated by moment-matching
techniques) of the linearized system; (2) we propose the concept of
normalized integral curve equations, which are repeatedly solved to
identify an almost-ideal manifold.
The manifold constructed by our algorithm inherits the important
property in [1] that it covers important system responses such as DC
and AC responses. It also preserves better local distance metrics on
the manifold, thanks to the employment of normalized integral curve
equations. To gauge the quality of the resulting manifold, we also
derive an error bound of the moments of linearized systems, assuming
moment- matching techniques are employed to generate low-order
subspaces for linearized systems. The algorithm is also more
systematic and generalizable to higher dimensions than the ad hoc
procedure in [1].
We illustrate the key ideas through a simple 2-D example. We also
combine this new manifold construction and parameterization algorithm
with maniMOR [1] to generate reduced models for a quadratic nonlinear
system and a CMOS circuit. Simulation results are provided, together
with comparisons to full models as well as TPWL reduced models [2]. |
| Slides |
| Title | A Fast Analog Mismatch Analysis by an Incremental and Stochastic Trajectory Piecewise Linear Macromodel |
| Author | *Hao Yu (Berkeley Design Automation, U.S.A.), Xuexin Liu, Hai Wang, Sheldon Tan (UC Riverside, U.S.A.) |
| Page | pp. 211 - 216 |
| Keyword | mismatch, stochastic differential-algebra-equation, nonlinear macromodel |
| Abstract | To cope with an increasing complexity when analyzing analog mismatch
in sub-90nm designs, this paper presents a fast non-Monte-Carlo
method to calculate mismatch in time domain.
The local random mismatch is described by a noise source
with an explicit dependence on geometric parameters,
and is further expanded by stochastic orthogonal polynomials (SOPs).
This forms a stochastic differential-algebra-equation (SDAE).
To deal with large-scale problems, the SDAE is linearized at
a number of snapshots along the nominal transient trajectory,
and hence is naturally embedded into a trajectory-piecewise-linear (TPWL) macromodeling.
The TPWL is improved with a novel incremental aggregation of subspaces
identified at those snapshots.
Experiments show that the proposed method, isTPWL, is
hundreds of times faster than Monte-Carlo method with a
similar accuracy. In addition, our macromodel further reduces
runtime by up to 25X, and is faster to build and more accurate
to simulate compared to existing approaches. |
| Slides |
| Title | Formal Verification of Tunnel Diode Oscillator with Temperature Variations |
| Author | *Kusum Lata, H S Jamadagni (CEDT,Indian Institute of Science, Bangalore, India) |
| Page | pp. 217 - 222 |
| Keyword | Analog and Mixed Signal Design, Formal Verification, Simulation, Hybrid Systems |
| Abstract | In this paper, we propose an extension to the formal verification approach of hybrid systems to verify the Tunnel Diode Oscillator (TDO) with temperature variations. This enables the same platform that is used for validating the hybrid system, to be also used to formally verify the Tunnel Diode Oscillator with temperature variations. The proposed approach utilizes the simulation traces from the actual implementation of the analog circuits to carry out the formal analysis and verification. We demonstrate our approach around Checkmate [1] and Tunnel diode Oscillator (TDO) as a case study. Current-Voltage simulations were performed on a tunnel diode and the basic feature of the I-V characteristics were analyzed in the temperature range 100-300K. TDO is designed and validated based on these characteristics. In particular, TDO has been verified formally for the continuous range of initial conditions at this temperature range. |