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The 15th Asia and South Pacific Design Automation Conference

Session 3D  Special Session: Recent Advancement in Post-silicon Validation
Time: 8:30 - 10:10 Wednesday, January 20, 2010
Location: Room 101D
Chair: Ing-Jer Huang (National Sun Yat-Sen University, Taiwan)

3D-1 (Time: 8:30 - 8:55)
Title(Invited Paper) Data Learning Based Diagnosis
Author*Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 247 - 254
Keyworddiagnostics, machine learning, rule induction, yield
AbstractThis paper illustrates a link between traditional perspective of diagnosis and a new perspective where diagnosis is seen as a form of data learning. We illustrate a diagnosis framework that employs various data learning techniques to implement two diagnosis approaches: feature ranking and rule extraction. We review the work that has been accomplished for implementing this framework and further discuss issues with its practical application.
Slides

3D-2 (Time: 8:55 - 9:20)
Title(Invited Paper) Using Introspective Software-based Testing for Post-silicon Debug and Repair
AuthorTodd Austin (Univ. of Michigan, U.S.A.)

3D-3 (Time: 9:20 - 9:45)
Title(Invited Paper) Post-silicon Debugging for Multi-core Designs
Author*Valeria Bertacco (Univ. of Michigan, U.S.A.)
Pagepp. 255 - 258
Keywordvalidation, post-silicon, multi-core
AbstractEscaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are recent trends towards chip multiprocessors (CMPs) with complex and sometimes on-deterministic memory subsystems prone to subtle, devastating bugs. This deteriorating situation is causing a growing portion of the validation effort to shift to post-silicon, when the first few hardware prototypes become available and where validation experiments are run directly on newly manufactured prototype hardware. In this work we first discuss the current needs of the industry in this space. We then overview some recent ideas developed in our research group to leverage the performance advantage of post-silicon validation, while sidestepping its limitations of low observability and debuggability. Finally we present some of today's general trends in post-silicon validation research.

3D-4 (Time: 9:45 - 9:57)
Title(Invited Paper) Low-cost Design for Repair with Circuit Partitioning
AuthorKyungho Kim, Byungtae Kang, Dongyun Kim (Samsung Electronics Co., Republic of Korea), Sungchul Lee, Juyong Shin, *Hyunchul Shin (Hanyang University, Republic of Korea)
Pagepp. 259 - 261
Keywordlow-cost, repair, partition
AbstractSilicon validation becomes difficult because of rapidly increasing complexity and operation speed of integrated circuits. When an error is found after a chip is fabricated, post-silicon repair is necessary. Full mask revision may significantly increase the cost and time-to-market. In this paper, we describe partial metal revision techniques in which only top-level metal layers are revised to fix “small” errors with minimal increase of the cost. When an error cannot be fixed by partial metal layer revision, full metal revision or full mask revision is necessary. However, frequently errors are small enough to be fixed by partial metal layer revision. Effective partitioning and pin-extension to top-level metal layers can significantly improve the repairability by using top-level metal revision.

3D-5 (Time: 9:57 - 10:09)
Title(Invited Paper) On Signal Tracing in Post-silicon Validation
Author*Qiang Xu, Xiao Liu (The Chinese University of Hong Kong, Hong Kong)
Pagepp. 262 - 267
KeywordVerification, Design, Trace-Based, Post-Silicon Validation
AbstractIt is increasingly difficult to guarantee the first silicon success for complex integrated circuit (IC) designs. Post-silicon validation has thus become an essential step in the IC design flow. Tracing internal signals during circuit's normal operation, being able to provide real-time visibility to the circuit under debug (CUD), is one of the most effective silicon debug techniques and has gained wide acceptance in industrial designs. Trace-based debug solution, however, involves non-trivial design for debug overhead. How to conduct signal tracing effectively for bug elimination is therefore a challenging task for IC designers. In this paper, we provide in-depth discussion for trace-based debug strategy and review recent advancements in this important area.