|Title||A Performance-Constrained Template-Based Layout Retargeting Algorithm for Analog Integrated Circuits|
|Author||Zheng Liu, *Lihong Zhang (Memorial University of Newfoundland, Canada)|
|Page||pp. 293 - 298|
|Keyword||Retargeting, Performance Sensitivity, Layout Parasitics, Piecewise, Constraints|
|Abstract||Performance of analog integrated circuits is highly sensitive to layout parasitics. This paper presents an improved template-based algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to achieve desired circuit performance, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies a piecewise-sensitivity model to control parasitic-related layout geometries by directly constructing a set of performance constraints subject to maximum performance deviation due to parasitics. The formulated problem is finally solved using graph-based techniques combined with mixed-integer nonlinear programming. The proposed method has been incorporated into a parasitic-aware automatic layout optimization and retargeting tool. It has been demonstrated to be effective and efficient especially when adapting layout design for new technologies or updated specifications.|
|Title||Symmetry-Aware TCG-Based Placement Design under Complex Multi-Group Constraints for Analog Circuit Layouts|
|Author||*Rui He, Lihong Zhang (Memorial University of Newfoundland, Canada)|
|Page||pp. 299 - 304|
|Keyword||placement, analog layout, symmetry constraints|
|Abstract||This paper presents a solution to handling complex multi-group symmetry constraints in the placement design using transitive closure graph (TCG) representation for analog layouts. We propose a set of symmetric-feasible conditions, which can automatically satisfy symmetry requirements. We also develop a new contour-based packing scheme with time complexity of O(g*n*lgn), where g is the number of symmetry groups and n is the number of the placed cells. Furthermore, we devise a set of perturbation operations with time complexity of O(n). Our experimental results show the effectiveness and superiority of this proposed scheme compared to the other state-of-the-art placement algorithms for analog layout design.|
|Title||Regularity-Oriented Analog Placement with Diffusion Sharing and Well Island Generation|
|Author||*Shigetoshi Nakatake (University of Kitakyushu, Japan), Masahiro Kawakita, Takao Ito (Toshiba Corp., Japan), Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki (NEC Micro Systems, Ltd., Japan)|
|Page||pp. 305 - 311|
|Keyword||analog placement, regularity-oriented, well island, diffusion sharing|
|Abstract||This paper presents
a novel regularity evaluation of placement structure
and MOS analog specific layout techniques
called diffusion sharing and well island generation,
which are developed based on Sequence-Pair.
The regular structures such as
topological row, array and repetitive structure
by the way of forming subsequences of a sequence-pair.
A placement objective is formulated
balancing the regularity and the area efficiency.
diffusion sharing and well island
can be also identified looking into forming of a sequence-pair.
we applied our regularity-oriented placement mixed with
the constraint-driven technique to real analog designs,
and attained the results comparable to manual designs
even when imposing symmetry constraints.
Besides, the results also revealed
the regularity serves to
increase row-structures applicable to the diffusion-sharing
for the area and wire-length saving.|
|Title||A Novel Characterization Technique for High Speed I/O Mixed Signal Circuit Components Using Random Jitter Injection|
|Author||*Ji Hwan (Paul) Chun (Intel Corporation, U.S.A.), Jae Wook Lee, Jacob A. Abraham (The University of Texas at Austin, U.S.A.)|
|Page||pp. 312 - 317|
|Keyword||Phase interpolator, High Speed I/O, Linearity, SerDes, DNL|
|Abstract||Timing problems in high-speed serial communications are mitigated with phase-interpolator (PI) circuitry. Linearity testing of PI has been challenging, even though PI is widely used in modern high speed I/O architectures. Previous research has focused on implementing additional built-in circuits to measure PI linearity. In this paper, we present a cost effective PI linearity measurement technique which requires no significant modification of existing I/O circuits. Our method uses jitter distributions obtained from random jitter injected into the data channel. Two distributions are separately obtained using undersampling and sampling using PI. The proposed algorithm calculates the differential nonlinearity (DNL) from the difference of these distributions. Simulation results show that the average prediction RMS error for the DNL calculation is 0.31 LSB.|