| Title | Checker-Pattern and Shared Two Pixels LOFIC CMOS Image Sensors |
| Author | *Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigetoshi Sugawa (Tohoku University, Japan) |
| Page | pp. 343 - 344 |
| Keyword | CMOS Image Sensor, high-resolution, Pixel Scailing, LOFIC |
| Abstract | Two wide dynamic range CMOS image sensors with lateral overflow integration capacitor have been developed. A checker-pattern image sensor has achieved high area efficiency by placing the color filters and on-chip microlens along the direction at an angle of 45-degree. A shared two pixels image sensor has achieved small pixel pitch by introducing a lateral overflow gate in each pixel. The fabricated image sensors exhibit high full well capacity, low noise, wide dynamic range and high resolution performance. |
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| Title | A CMOS Image Sensor With 2.0-e- Random Noise and 110-ke- Full Well Capacity Using Column Source Follower Readout Circuits |
| Author | *Takahiro Kohara, Wonghee Lee (Graduate School of Engineering, Tohoku University, Japan), Koichi Mizobuchi (DISP Development, Texas Instruments Japan, Japan), Shigetoshi Sugawa (Graduate School of Engineering, Tohoku University, Japan) |
| Page | pp. 345 - 346 |
| Keyword | CMOS image sensor, Column amplifier, noise, full well capacity, lateral overflow integration |
| Abstract | A low noise CMOS image sensor without degradation of saturation performance has been developed by using column amplifiers of the gains of about 1.0 in a lateral overflow integration capacitor technology. The 1/4-inch, SVGA CMOS image sensor has achieved 0.98 column readout gain, 100-uV/e- conversion gain, 2.0-e- total random noise, 0.5-e- in readout circuits, 110,000-e- full well capacity and 95-dB dynamic range. Moreover, we measure the pixel noises by using developed readout circuits and optimize pixel operating condition. |
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| Title | Checkered White-RGB Color LOFIC CMOS Image Sensor |
| Author | *Shun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa (Tohoku University, Japan) |
| Page | pp. 347 - 348 |
| Keyword | high sensiivity, wide dynamic range, White-RGB, LOFIC, CMOS |
| Abstract | We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1/3.3-inch optical format, 1280(H) x 480(V) pixels, 4.2-um effective pixel pitch along with 45-degree direction was designed and fabricated through 0.18-um 2-Poly 3-Metal CMOS technology with buried pinned photodiode process. The image sensor has achieved about 108-uV/e- high conversion gain and about 102-dB dynamic range performance in one exposure. |
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| Title | A Versatile Recognition Processor for Sensor Network Applications |
| Author | *Risako Takashima, Hanai Yuya, Yuichi Hori, Tadahiro Kuroda (Keio University, Japan) |
| Page | pp. 349 - 350 |
| Keyword | detection, recognition, wireless sensor network, Haar-like feature |
| Abstract | A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy dissipation of sub-mJ/frame. The versatility and the energy efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier. |
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| Title | A 2-6 GHz Fully Integrated Tunable CMOS Power Amplifier for Multi-Standard Transmitters |
| Author | Daisuke Imanishi, *JeeYoung Hong, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 351 - 352 |
| Keyword | Power amplifier, CMOS, tunable, multi-band, SDR |
| Abstract | A tunable power amplifier (PA) from 2.1GHz to 6.0GHz is presented for multi-standard radios. The proposed multi-band PA can tune the output impedance to 50Ohm over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18um CMOS process, and the supply voltage is 3.3V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than -8dB, power gain of larger than 12dB, output 1-dB compression point of larger than 15dBm. |
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| Title | An Embedded Debugging/Performance Monitoring Engine for a Tile-based 3D Graphics SoC Development |
| Author | *Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang (National Sun Yat-Sen University, Taiwan) |
| Page | pp. 353 - 354 |
| Keyword | 3D graphics, Debugging, Performance monitoring, Bus protocol checker, Bus tracer |
| Abstract | This paper presents an embedded debugging/ performance monitoring engine (EDPME), which is capable of collect run time characteristics, detect AHB on-chip bus protocol error/inefficiency, and capture on-chip AHB bus traces at various abstraction levels with compression ratio up to 98% for a low cost tile-based 3D graphics SoC development. |
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| Title | Cascaded Time Difference Amplifier using Differential Logic Delay Cell |
| Author | *Shingo Mandai (The University of Tokyo, Japan), Toru Nakura, Makoto Ikeda, Kunihiro Asada (VLSI Design and Education Center(VDEC), The University of Tokyo, Japan) |
| Page | pp. 355 - 356 |
| Keyword | Time Difference Amplifier, Time Amplifier, TOF, TDC |
| Abstract | We introduce a 4x4 cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18um CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and 250ps input range. |
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| Title | Built-in Self At-Speed Delay Binning and Calibration Mechanism in Wireless Test Platform |
| Author | Chen-I Chung, Jyun-Sian Jhou, *Ching-Hwa Cheng (Feng Chia University, Taiwan) |
| Page | pp. 357 - 358 |
| Keyword | at-speed delay test, Built-In Self Test (BIST) |
| Abstract | An at-speed BIST delay testing technique is proposed. It differs from traditional circuit speed testing techniques by changing the system clock rate. This method supplies test pattern to the circuit using lower-speed clock frequency, then applies internal BIST circuit to adjust clock edge for circuit at-speed delay testing and speed binning. The self wide-range (26%~76%), fine-scale (34ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit is proposed for at-speed delay test and performance binning. The contribution of this work is the proposal of a feasible self at-speed delay testing technique. Test chip DFT strategies are fully validated by instruments and HOY wireless test system. Key words: scan based delay testing, at speed testing, speed binning |
| Title | Dynamic Voltage Domain Assignment Technique for Low Power Performance Manageable Cell Based Design |
| Author | Elone Lee, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia University, Taiwan), Jiun-In Guo (National Chung Cheng University, Taiwan) |
| Page | pp. 359 - 360 |
| Keyword | multi voltage, voltage domain, performance-power manageable |
| Abstract | Multi-voltage technique is an effective way to reduce power consumption. In the proposed voltage domain programmable (VDP) technique, high and low voltage domains applied to logic gates are programmable. The different voltage domains allow the chip performance and power consumption to be flexibly adjusted during circuit operation. In this proposed internal of the chip technique, the power switches possess the feature of flexible programming after chip manufacturing. The video decoder test chip proof of this novel methodology has 55% power reduction with good power-performance management mechanism. |
| Title | Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits |
| Author | *Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka University, Japan) |
| Page | pp. 361 - 362 |
| Keyword | subthreshold circuit, manufacturing variability, body biasing |
| Abstract | This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using "canary flip-flop" that can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65nm CMOS process. Measurement results show that the adaptive control can reduce the power dissipation by 46% in comparison with the worst-case design with guardbanding. |
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| Title | A 60GHz Direct-Conversion Transmitter in 65nm CMOS Technology |
| Author | *Naoki Takayama, Kouta Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 363 - 364 |
| Keyword | transmitter, mm-wave, CMOS, power amplifier |
| Abstract | This paper presents a 60 GHz direct-conversion transmitter in 65 nm CMOS technology. The power amplifier consists of 4-stage transistors. The circuit model of de-coupling capacitor is built as a transmission line to consider the physical length. In the measurement results, the conversion gain is above 9.6dB at 58-65GHz band, and the 1 dB compression point is 1.6 dBm with 60 GHz LO frequency and 1 dB LO power. |
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| Title | An Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function |
| Author | *Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura (Kyushu Institute of Technology, Japan) |
| Page | pp. 365 - 366 |
| Keyword | 3-terminal, regulator, serial, control, adjustment |
| Abstract | This paper describes a new technique for 3-terminal regulators to adjust the output voltage level without additional terminals or extra off-chip components. By applying a serial control pattern using the intermediate voltage level between the supply voltage and the regulator output, the adjustment data in the internal nonvolatile memory are safely updated without noise disturbance. In an on-board test with a chip fabricated using a 0.35-um standard CMOS process, we confirm successful output voltage adjustment with sub-10mV precision. |
| Title | Fine Resolution Double Edge Clipping with Calibration Technique for Built-In At-Speed Delay Testing |
| Author | Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia University, Taiwan) |
| Page | pp. 367 - 368 |
| Keyword | at speed delay test, built-in self test, lunch off capture |
| Abstract | At speed Built-In Self Test (BIST) circuit can solve many test challenges generated from traditionally slower Automatic Test Equipment (ATE). In this paper, a double edge clipping technique is proposed for built-in at-speed delay testing requirements. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST technique to adjust clock edges for circuit at-speed delay testing and speed binning. Test chips are fully validated. The fine-scale (16ps) progressive capture edge adjustment technique with high-precision (28ps) calibration circuit is effective for at-speed delay testing and performance binning. |
| Title | Geyser-1: A MIPS R3000 CPU core with fine-grained run-time Power Gating |
| Author | Diasuke Ikebuchi, Naomi Seki, Yuu Kojima, *Masahiro Kamata, Zhao Lei, Hideharu Amano (Keio University, Japan), Toshiki Shirai, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Hiroki Masuda, Kimiyoshi Usami (Shibaura Institute of Technology, Japan), Seidai Takeda, Hiroshi Nakamura (University of Tokyo, Japan), Mitaro Namiki (University of Agriculture and Technology, Japan), Masaaki Kondo (The University of Electro-Communications, Japan) |
| Page | pp. 369 - 370 |
| Keyword | CPU, Power Gating, Low leakage power |
| Abstract | Geyser-1, a prototype MIPS R3000 CPU with fine-grained runtime PG for major computational components in the execution stage is available. Function units such as ALU, shifter, multiplier and divider are power-gated and controlled in runtim such that only the function nit to be used in an instruction is powerd-on to minimize the leakage power. The evaluation results with the real chip reveals that the fine-grained runtime PG mechanism works at least 60MHz clock without electric problems. It reduces the leakage power 7% at 25 centigrade and 24% at 80 centigrade. The evaluation using benchmark programs show that the consuming power can be reduced from 3% at 25 centigrade and 30% at 80 centigrade. |
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| Title | A WiMAX Turbo Decoder with Tailbiting BIP Architecture |
| Author | *Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku University, Japan), Hisanori Fujisawa (Fujitsu Laboratories Ltd., Japan), Takashi Ito (Tohoku University, Japan) |
| Page | pp. 371 - 372 |
| Keyword | WiMAX, turbo decoder, tailbiting, block-interleaved pipelining (BIP), Max-Log-MAP |
| Abstract | A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm2 using a 0.18 mm CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation. |
| Title | Temporal Circuit Partitioning for a 90nm CMOS Multi-Context FPGA and its Delay Measurement |
| Author | *Naoto Miyamoto, Tadahiro Ohmi (Tohoku University, Japan) |
| Page | pp. 373 - 374 |
| Keyword | multi-context FPGA, execution latency, temporal partitioning, temporal communication |
| Abstract | In this paper, we present a multi-context FPGA named Flexible Processor (FP) and its execution delay measurement results. A temporal partitioning algorithm for the FP has been developed, which divides a long critical path into equal-length shorter paths. The FP has been designed and fabricated by using a 90nm CMOS technology. From the measurement results, the execution latency remains constant regardless of the number of contexts used. |
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| Title | Design and Chip Implementation of an Instruction Scheduling Free Ubiquitous Processor |
| Author | *Masa-aki Fukase, Ryosuke Murakami, Tomoaki Sato (Hirosaki University, Japan) |
| Page | pp. 375 - 376 |
| Keyword | Ubiquitous Processor, CMOS chip |
| Abstract | Instruction scheduling is a crucial issue for cutting edge VLSI processors that exploit parallelism to achieve power conscious high performance. A double scheme that merges scalar units into a multifunctional unit (MFU) and makes resultant MFU wave-pipeline achieves instruction scheduling free ILP (instruction level parallelism). Applying the double scheme to chip design, the latest chip of the ubiquitous processor architecture, HCgorilla is implemented by using 0.18-um CMOS standard cell technology. |
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| Title | MUCCRA-3: A Low Power Dynamically Reconfigurable Processor Array |
| Author | Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, *Masayuki Kimura, Hideharu Amano (Keio University, Japan) |
| Page | pp. 377 - 378 |
| Keyword | dynamically reconfigurable |
| Abstract | MuCCRA-3 is a low power coarse-grained Dynamically Reconfigurable Processor Array (DRPA) for a flexible off-loading engine in various SoC(System-on-a-Chip). Similar to the other DRPAs, it has an array of processing elements (PEs), a simple coarse-grained processor, consisting of an ALU and a register file, and dynamic reconfiguration of the array enables time-multiplexed execution. For low power computation, the PE array structure of MuCCRA-3 is optimized according to the evaluation results of previous prototypes, MuCCRA-1 and 2[1], and was implemented with 65nm low power CMOS process from Fujitsu. By using a real chip, the power consumption and performance are evaluated. The evaluation results suggest that MuCCRA-3 works with extremely low power. |
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| Title | Rapid Prototyping on a Structured ASIC Fabric |
| Author | *Steve C.L. Yuen, Yan-Qing Ai, Brian P.W. Chan (Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong), Thomas C.P. Chau (Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong), Sam M.H. Ho, Oscar K.L. Lau, Kong-Pang Pun (Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong), Philip H.W. Leong (School of Electrical and Information Engineering, University of Sydney, Australia), Oliver C.S. Choy (Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 379 - 380 |
| Keyword | structured ASIC, metal programmable fabric, rapid prototyping, cell design, tool integration |
| Abstract | We describe the architecture of a structured ASIC fabric in which the logic and routing can be customized using three masks. A standard Cadence based design flow is employed, and using an active dynamic backlight controller as an example, performance is compared to that of an ASIC implementation in the same technology. |
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| Title | A High Performance Low Complexity Joint Transceiver for Closed-Loop MIMO Applications |
| Author | Jian-Lung Tzeng, Chien-Jen Huang, *Yu-Han Yuan, Hsi-Pin Ma (National Tsing Hua University, Taiwan) |
| Page | pp. 381 - 382 |
| Keyword | Closed-Loop MIMO, Baseband Signal Processing, FPGA implementation |
| Abstract | An efficient and practicable MIMO transceiver in which transmitter antenna selection is applied to QR detector and GMD precoding through limited feedback channel is implemented. For over 4x5 antenna selection, the proposed antenna selection scheme can save more than 50% computational complexity compared with that of the exhausting method. From the simulation results, the proposed transceiver can achieve over 6 dB SNR improvement over the open-loop V-BLAST counterparts at BER=10-2 under i.i.d. channel. Finally, a MIMO joint transceiver hardware platform on a Xilinx FPGA is realized to verify the proposed algorithm and architecture. |
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