| Title | Scan-Based Attack against Elliptic Curve Cryptosystems |
| Author | *Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda University, Japan) |
| Page | pp. 407 - 412 |
| Keyword | scan path, scan-based attack, elliptic curve cryptosystem, LSI |
| Abstract | Scan-based attacks are techniques to decipher a secret key using
scanned data obtained from a cryptography circuit.
Public-key cryptography, such as RSA and elliptic curve cryptosystem (ECC),
is extensively used but conventional scan-based attacks cannot be applied to it,
because it has a complicated algorithm as well as a complicated architecture.
This paper proposes a scan-based attack which enables us to decipher a
secret key in ECC.
The proposed method is based on detecting intermediate values
calculated in ECC.
By monitoring the 1-bit sequence in the
scan path, we can find out the register position specific to the
intermediate value in it and we can know whether this intermediate
value is calculated or not in the target ECC circuit. By using several
intermediate values, we can decipher a secret key.
The experimental results demonstrate that a secret key in a practical
ECC circuit can be deciphered using 29 points over the elliptic curve E
within 40 seconds. |
| Slides |
| Title | Secure and Testable Scan Design Using Extended de Bruijn Graphs |
| Author | Hideo Fujiwara, *Marie Engelene J. Obien (Nara Institute of Science and Technology, Japan) |
| Page | pp. 413 - 418 |
| Keyword | Secure scan design, security, testability, design for test, extended de Bruijn graph |
| Abstract | In this paper, we first introduce extended de Bruijn graphs to design extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. Using the extended shift registers, we present a new secure and testable scan design approach that aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan registers to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. New concepts of scan security and scan testability are also introduced. |
| Slides |
| Title | Correlating System Test Fmax with Structural Test Fmax and Process Monitoring Measurements |
| Author | *Chia-Ying (Janine) Chen (University of California, Santa Barbara, U.S.A.), Jing Zeng (Advanced Micro Devices, Inc, U.S.A.), Li-C. Wang (University of California, Santa Barbara, U.S.A.), Michael Mateja (Advanced Micro Devices, Inc, U.S.A.) |
| Page | pp. 419 - 424 |
| Keyword | correlation analysis, data learning approach, system test, structural test |
| Abstract | System test has been the standard measurement to evaluate performance variability of high-performance microprocessors. The question of whether or not many of the lower-cost alternative tests can be used to reduce system test has been studied for many years. This paper utilizes a data-learning approach for correlating three test datasets, structural test, ring oscillator test, and scan flush test, with system test. With the data-learning approach, higher correlation can be found without altering test measurements or test conditions. Rather, the approach utilizes new optimization algorithms to extract more useful information in the three test datasets, with particular success using the structural test data. To further minimize test cost, process monitoring measurements (ring oscillator and scan flush tests) are used to reduce the need for high-frequency structural test. We demonstrate our methodology on a recent high-performance microprocessor design. |
| Slides |