| Title | Optimizing Power and Performance for Reliable On-Chip Networks |
| Author | Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, *Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan (The Pennsylvania State University, U.S.A.) |
| Page | pp. 431 - 436 |
| Keyword | Network-on-chip, Error Correction Code, Architectural Vulnerability Factor, residual error rate, throttling |
| Abstract | We propose novel techniques to minimize the power and performance penalties in protecting the NoC against soft errors, while giving desired reliability guarantees. Some applications have inherent error tolerance which can be exploited to save power, by turning off the error correction mechanisms for a fraction of the total time without trading off reliability. To further increase the power savings, we bound the vulnerability of a router by throttling the traffic into the router. In order to minimize the throughput loss due to throttling, we propose dividing the die into domains and using multiple vulnerability bounds across these domains. We explore both static and dynamic selection of vulnerability bounds. We find that for applications with an error tolerance of 10% of the raw error rate, the dynamic multiple vulnerability bound scheme can save up to 44% of power expended for error correction at a marginal network throughput loss of 3%. |
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| Title | Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs |
| Author | Tsung-Yi Wu (National Changhua University of Education, Taiwan), How-Rern Lin (Providence University, Taiwan), Tzi-Wei Kao, *Shi-Yi Huang, Tai-Lun Li (National Changhua University of Education, Taiwan) |
| Page | pp. 444 - 449 |
| Keyword | IP-based SoC Design, IR Drop, Clock Scheme, Handshaking Protocol, Virtual Component Interface |
| Abstract | In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the number of power and ground pads for preventing voltage drop problem. The number of aggregate switching gates can be shortened if the SoC design can use a clock scheme of mixed positive and negative triggering edges rather than one of pure positive (negative) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce the peak current up to 56.3%. Our technique also can be applied to a level sensitive design. |
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| Title | Workload Capacity Considering NBTI Degradation in Multi-core Systems |
| Author | Jin Sun, Roman Lysecky, Karthik Shankar (The University of Arizona, U.S.A.), Avinash Kodi (Ohio University, U.S.A.), Ahmed Louri, *Janet M. Wang (The University of Arizona, U.S.A.) |
| Page | pp. 450 - 455 |
| Keyword | Multi-core Systems, Negative Bias Temperature Instability, Mean-Time-To-Failure, Workload Balancing |
| Abstract | As device feature sizes continue to shrink, long-term reliability such as Negative Bias Temperature Instability (NBTI) leads to low yields and short mean-time-to-failure (MTTF) in multi-core systems. This paper proposes a new workload balancing scheme based on device level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. The proposed method employs the Capacity Rate (CR) provided by the NBTI model, applies Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on 64-core system show that by allowing a small part of the cores to relax over a short time period (10 seconds), the proposed methodology improves multi-core system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%). |
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