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The 15th Asia and South Pacific Design Automation Conference

Session 5D  Designers' Forum: State-of-the-art SoCs
Time: 13:30 - 15:10 Wednesday, January 20, 2010
Location: Room 101D
Organizers: Kunio Uchiyama (Hitachi, Japan), Ing-Jer Huang (National Sun Yat-Sen University, Taiwan)

5D-1 (Time: 13:30 - 13:55)
Title(Invited Paper) Overview of ITRI's Parallel Architecture Core (PAC) DSP Project: from VLIW DSP Processor to Android-ready Multicore Computing Platform
Author*An-Yeu (Andy) Wu (STC/ITRI, Taiwan)
KeywordVLIW, DSP, parallel architecture, SoC, multimedia
AbstractThe Industrial Technology Research Institute (ITRI) PAC (Parallel Architecture Core) project was initiated in 2003. The target is to develop a low-power and high-performance programmable platform for multimedia applications. In the first PAC project phase (2004~2006), a 5-way VLIW DSP (PACDSP) processor has been developed with our patented distributed & ping-pong register file and variable-length VLIW encoding techniques. Recently, a tri-core PACDSP-based SoC, PAC-Duo (ARM9 + two DSP Cores), has also been designed and fabricated in TSMC 90nm technology to demonstrate the multicore-based outstanding performance and energy efficiency for multimedia processing such as real-time H.264 codec. In addition, to link with Web-based services, the Google Android software stack and OpenCore-based multimedia library are successfully implemented and verified in PAC-Duo SoC. To assist with architectural exploration of next-generation PAC-Duo SoC (PAC-Duo+), Electronic System Level (ESL) analysis with power information is also conducted. The future direction of ITRI multicore project planning will also be addressed in this presentation.

5D-2 (Time: 13:55 - 14:20)
Title(Invited Paper) Design and Verification Methods of Toshiba's Wireless LAN Baseband SoC
Author*Masanori Kuwahara (Toshiba, Japan)
Pagepp. 457 - 463
Keywordwireless LAN, MAC, PHY, low power, verification
AbstractThis paper presents design and verification methods of Toshiba's wireless LAN (WLAN) baseband SoCs. An FPGA-based high-speed and reliable verification environment for physical layer (PHY), a new SDL-based hardware design method for media access control layer (MAC), and an ultra low power design resulting in power consumption of 22 uW in the deep-sleep mode are described.
Slides

5D-3 (Time: 14:20 - 14:45)
Title(Invited Paper) Programmable Platform for Multimedia SoC
Author*Bor-Sung Liang (Sunplus Core Technology, Taiwan)
Keywordmultimedia platform, SoC
AbstractNowadays SoC development suffers from high R&D cost. High system complexity and mask costs make R&D expense worse dramatically. Moreover, current multimedia SoCs need to support lots of video/audio CODEC formats. In order to solve the problems, SoC with programmability can provide flexibility to retarget various applications to share R&D cost, and easier to meet time-to-market and time-in-market requirements. In this talk we will share some experiences on programmable platform for multimedia platform.

5D-4 (Time: 14:45 - 15:10)
Title(Invited Paper) SOC for Car Navigation Systems with a 55.3 GOPS Image Recognition Engine
Author*Hiroyuki Hamasaki, Yasuhiko Hoshi, Atsushi Nakamura, Akihiro Yamamoto (Renesas Technology, Japan), Hideaki Kido, Shoji Muramatsu (Hitachi Ltd, Japan)
Pagepp. 464 - 465
KeywordSoC, image recognition, car navigation systems
AbstractThis paper introduces the System on a Chip (SOC) equipped with dual RISC processors, an image recognition engine operating with up to 55.3 GOPS, multiple accelerators and peripherals for car navigation systems. The SoC has high performance with respect to image recognition applications which are installed in advanced vehicles as well as navigation function such as graphics operating at the same time. Furthermore we have developed the SoC in order to meet automotive specifications including cost and size. We report practical application which is for the pedestrian detection to demonstrate our SoC capability. We accelerate the application with combination of the RISC processor and image recognition engine.
Slides