Title | (Invited Paper) Overview of ITRI's Parallel Architecture Core (PAC) DSP Project: from VLIW DSP Processor to Android-ready Multicore Computing Platform |
Author | *An-Yeu (Andy) Wu (STC/ITRI, Taiwan) |
Keyword | VLIW, DSP, parallel architecture, SoC, multimedia |
Abstract | The Industrial Technology Research Institute (ITRI) PAC (Parallel Architecture Core) project was initiated in 2003. The target is to develop a low-power and high-performance programmable platform for multimedia applications. In the first PAC project phase (2004~2006), a 5-way VLIW DSP (PACDSP) processor has been developed with our patented distributed & ping-pong register file and variable-length VLIW encoding techniques. Recently, a tri-core PACDSP-based SoC, PAC-Duo (ARM9 + two DSP Cores), has also been designed and fabricated in TSMC 90nm technology to demonstrate the multicore-based outstanding performance and energy efficiency for multimedia processing such as real-time H.264 codec. In addition, to link with Web-based services, the Google Android software stack and OpenCore-based multimedia library are successfully implemented and verified in PAC-Duo SoC. To assist with architectural exploration of next-generation PAC-Duo SoC (PAC-Duo+), Electronic System Level (ESL) analysis with power information is also conducted. The future direction of ITRI multicore project planning will also be addressed in this presentation. |
Title | (Invited Paper) SOC for Car Navigation Systems with a 55.3 GOPS Image Recognition Engine |
Author | *Hiroyuki Hamasaki, Yasuhiko Hoshi, Atsushi Nakamura, Akihiro Yamamoto (Renesas Technology, Japan), Hideaki Kido, Shoji Muramatsu (Hitachi Ltd, Japan) |
Page | pp. 464 - 465 |
Keyword | SoC, image recognition, car navigation systems |
Abstract | This paper introduces the System on a Chip (SOC) equipped with dual RISC processors, an image recognition engine operating with up to 55.3 GOPS, multiple accelerators and peripherals for car navigation systems. The SoC has high performance with respect to image recognition applications which are installed in advanced vehicles as well as navigation function such as graphics operating at the same time. Furthermore we have developed the SoC in order to meet automotive specifications including cost and size. We report practical application which is for the pedestrian detection to demonstrate our SoC capability. We accelerate the application with combination of the RISC processor and image recognition engine. |
Slides |