| Title | Application-Specific 3D Network-on-Chip Design Using Simulated Allocation |
| Author | Pingqiang Zhou (University of Minnesota, U.S.A.), Ping-Hung Yuh (National Taiwan University, Taiwan), *Sachin S. Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 517 - 522 |
| Keyword | 3D, Networks on chip (NoC), floorplanning, topology synthesis, application-specific NoCs |
| Abstract | Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%). |
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| Title | A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip |
| Author | Wooyoung Jang, *David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 523 - 528 |
| Keyword | Networks-on-chip, Multiprocessor System-on-Chip, Task mapping, Homogeneous/heterogeneous core |
| Abstract | In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) not only with homogeneous cores on regular mesh architecture as done by most previous mapping algorithms but also with heterogeneous cores on irregular mesh or custom architecture. As a main contribution, we develop a simple yet efficient interconnection matrix that models any task graph and network. Then, task mapping problem is exactly formulated to an MIQP (Mixed Integer Quadratic Programming). Since MIQP is NP-hard [14], we propose two effective heuristics, a successive relaxation algorithm and a genetic algorithm. Experimental results show that A3MAP by the successive relaxation algorithm reduces an amount of traffic up to 5.7%, 16.1% and 7.3% on average in regular mesh, irregular mesh and custom network, respectively, compared to the previous state-of-the-art work [1]. A3MAP by the genetic algorithm reduces more traffic up to 8.8%, 29.4% and 16.1 % on average than [1] in regular mesh, irregular mesh and custom network, respectively even if its runtime is longer. |
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| Title | Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip |
| Author | *Jonas Diemer, Rolf Ernst (Institute of Computer and Network Engineering, TU Braunschweig, Germany), Michael Kauschke (Intel, Germany) |
| Page | pp. 529 - 534 |
| Keyword | Network-on-Chip, Quality-of-Service, MPSoC, Best-Effort, Low-Latency |
| Abstract | Networks-on-chip (NoC) for future multi- and many-core processor platforms face an increasing diversity of traffic requirements, ranging from streaming traffic with real-time requirements to bursty best-effort. The best-effort traffic usually results from applications running on general-purpose processors with caches and is very sensitive to latency. Hence, the NoC must provide guaranteed services to some traffic streams, while maintaining low latency and high throughput of best-effort traffic. In this paper, we propose a run-time configurable NoC that enables bandwidth guarantees with minimum impact on latency for best-effort traffic. This is achieved by prioritization and distributed traffic shaping of best-effort traffic. The analysis and evaluation of our quality-of-service scheme show that it can provide tight bandwidth guarantees for streaming traffic. At the same time, the average latencies of best-effort traffic improved by up to 47% compared to a standard prioritization scheme. |
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| Title | Floorplanning and Topology Generation for Application-Specific Network-on-Chip |
| Author | *Bei Yu, Sheqin Dong (Tsinghua University, China), Song Chen, Satoshi Goto (Waseda University, Japan) |
| Page | pp. 535 - 540 |
| Keyword | Networks-on-Chip, partition driven floorplanning, switches insertion, network interfaces insertion, path allocation |
| Abstract | Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving. |
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