| Title | An Analytical Dynamic Scaling of Supply Voltage and Body Bias Exploiting Memory Stall Time Variation |
| Author | *Jungsoo Kim, Younghoon Lee (KAIST, Republic of Korea), Sungjoo Yoo (POSTECH, Republic of Korea), Chong-Min Kyung (KAIST, Republic of Korea) |
| Page | pp. 575 - 580 |
| Keyword | DVFS, energy optimization, runtime distribution, memory stall |
| Abstract | Success of workload prediction, which is critical in achieving low energy consumption via dynamic voltage and frequency scaling (DVFS), depends on the accuracy of modeling the major sources of workload variation. Among them, memory stall time, whose variation is significant especially in case of memory-bound applications, has been mostly neglected or handled in too simplistic assumptions in previous works. In this paper, we present an analytical DVFS method which takes into account variations in both computation and memory stall cycles. The proposed method reduces leakage power consumption as well as switching power consumption through combined Vdd/Vbb scaling. Experimental results on MPEG4 and H.264 decoder have shown that, compared to previous methods, our method achieves up to additional 30.0% and 15.8% energy reductions, respectively. |
| Slides |
| Title | Bounded Potential Slack: Enabling Time Budgeting for Dual-Vt Allocation of Hierarchical Design |
| Author | *Jun Seomun, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea) |
| Page | pp. 581 - 586 |
| Keyword | Hierarchical design, slack, budgeting, dual-Vt, leakage |
| Abstract | Time budgeting, which assigns timing assertion at block boundary, is a crucial step in hierarchical design. The proportion of high- and low-Vt gates of each block, which determines overall leakage power consumption, is dictated by timing assertion, yet dual-Vt allocation is not taken into account during conventional time budgeting. Bounded potential slack is introduced as a measure of dual-Vt allocation, and is experimentally shown to be strongly correlated with the percentage of high-Vt gates. A new time budgeting is proposed with objective of achieving bounded potential slack, which is formulated as a linear programming problem. In experiments with example hierarchical designs implemented in 45-nm commercial technology, the proposed time budgeting reduced leakage power by 32% on average compared to conventional time budgeting, when both are followed by the same dual-Vt allocation. The time budgeting is also applied to voltage island design, where each block can have its own Vdd with mix of high- and low-Vt gates. |
| Slides |
| Title | Dynamic Power Estimation for Deep Submicron Circuits with Process Variation |
| Author | Quang Dinh, *Deming Chen, Martin Wong (UIUC, U.S.A.) |
| Page | pp. 587 - 592 |
| Keyword | Dynamic Power, Process Variation, Statistical Design, Power Estimation |
| Abstract | Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow glitches consume less power than wide glitches. Glitch width and transition density modeling is further complicated by the effect of process variation. This paper presents a fast and accurate dynamic power estimation method that considers the detailed effect of process variation. First, we extend the probabilistic modeling approach to handle timing variations. Then the power consumption of a logic gate is computed based on the transition waveforms of its inputs. Both mean values and standard deviations of the dynamic power are estimated with high confidence based on accurate device characterization data. Compared with SPICE-based Monte Carlo simulations for small circuits, our power estimator reports power results within 3% error for the mean and 5% error for the standard deviation with six orders of magnitude speedup. For medium and large benchmarks, it is impossible to run Monte Carlo simulations with enough samples due to very long runtime, while our estimator can finish within minutes. |
| Slides |
| Title | Runtime Temperature-Based Power Estimation for Optimizing Throughput of Thermal-Constrained Multi-Core Processors |
| Author | Dongkeun Oh, Nam Sung Kim, Yu Hen Hu (University of Wisconsin, U.S.A.), *Charlie Chung Ping Chen (National Taiwan University, Taiwan), Azadeh Davoodi (University of Wisconsin, U.S.A.) |
| Page | pp. 593 - 599 |
| Keyword | thermal sensor, optimization |
| Abstract | Technology scaling has allowed integration of multiple cores into a single die. However, high power consumption of each core leads to very high heat density, limiting the throughput of thermal-constrained multi-core processors. To maximize the throughput, various software-based dynamic thermal management and optimization techniques have been proposed, many of which depend on accurate temperature sensing of each core. However, the decision for dynamic thermal management and throughput optimization only based on the temperature of each core can result in less optimal throughput in certain circumstances according to our investigation. In this paper, we propose 1) a dynamic power estimation method using a single thermal sensor for each core in multi-core processors, 2) a die temperature reconstruction method using the estimated power, and 3) a throughput optimization method based the estimated power instead of the temperature. According to our experiment using 90nm technology, the proposed method results in less than 3% error in estimating power and hot-spot temperature of a multi-core processor. Furthermore, the proposed throughput optimization method based on the estimated power leads to up to 4% higher throughput than a temperature-based optimization method. |