Title | (Invited Paper) Resilient Design in Scaled CMOS for Energy Efficiency |
Author | James Tschanz, Keith Bowman, Muhammad Khellah, Chris Wilkerson, Bibiche Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, *Vivek K. De (Intel Corporation, U.S.A.) |
Page | p. 625 |
Keyword | Resiliency, Variations |
Abstract | Opportunites for resiliency to improve energy efficiency of processor designs in scaled CMOS technologies are discussed. |
Slides |
Title | (Invited Paper) Benefits and Barriers to Probabilistic Design |
Author | *Siva Narendra (Tyfone, Inc./Portland State University, U.S.A.) |
Page | pp. 626 - 627 |
Keyword | CMOS variation and leakage, Probabilistic Design, Adaptive design, Stochastic design |
Abstract | The undisputed increase in IOFF and large variations in IOFF – combined with ION/IOFF ratio approaching unity – leads to transistors that become increasing unreliable and unpredictable switches. A more comprehensive motivation is made on why therefore there are compelling benefits to design based on probabilistic methods. However, given the maturity of our industry, it is more likely that this will be realized in evolutionary steps toward such an ultimate change in our design and thought process. While this is a barrier for revolutionary innovation, it is likely the best possible mode for widespread commercial success. A potential three phase evolutionary roadmap towards that ultimate true probabilistic design is presented as well. |
Title | (Invited Paper) A Probabilistic Boolean Logic for Energy Efficient Circuit and System Design |
Author | Lakshmi N. B. Chakrapani (Rice University, U.S.A.), *Krishna Palem (Rice University/Nanyang Technological University, U.S.A.) |
Page | pp. 628 - 635 |
Abstract | We introduce probabilistic design, a methodology to design circuits using gates with probabilistic behavior. Probabilistic design is of great value, since the international technology roadmap for semiconductors (ITRS) forecasts that devices and interconnect are likely to suffer from frequent transient and permanent failures, as a consequence of technology scaling. We first provide the theoretical basis for probabilistic design, rooted in a novel Probabilistic Boolean Logic (PBL). By combining the properties of PBL with the properties of noise susceptible CMOS devices, we derive design principles and demonstrate that probabilistic design is a viable methodology to design circuits using gates with probabilistic behavior, which has been shown to be a useful approach for implementing ultra low-energy circuit designs. |
Title | (Panel Discussion) Dependable Silicon Design with Unreliable Components |
Author | Organizer & Moderator: Vincent Mooney (Georgia Institute of Technology/Nanyang Technological University, U.S.A.), Panelists: Vivek K. De (Intel Corporation, U.S.A.), Siva Narendra (Tyfone, Inc., U.S.A.), Krishna Palem (Rice University/Nanyang Technological University, U.S.A.) |