(Back to Session Schedule)

The 15th Asia and South Pacific Design Automation Conference

Session 8D  Special Session: ESL: Analysis and Synthesis of Multi-core Systems
Time: 10:30 - 12:10 Thursday, January 21, 2010
Location: Room 101D
Organizer & Chair: Daniel D. Gajski (University of California, Irvine, U.S.A.)

8D-1 (Time: 10:30 - 10:55)
Title(Invited Paper) Computer-aided Recoding for Multi-core Systems
Author*Rainer Doemer (University of California, Irvine, U.S.A.)
Pagepp. 713 - 716
KeywordEmbedded Systems, System Design, Modeling, Recoding
AbstractThe design of embedded computing systems faces a serious productivity gap due to the increasing complexity of their hardware and software components. One solution to address this problem is the modeling at higher levels of abstraction. However, manually writing proper executable system models is challenging, error-prone, and very time-consuming. We aim to automate critical coding tasks in the creation of system models. This paper outlines a novel modeling technique called computer-aided recoding which automates the process of writing abstract models of embedded systems by use of advanced computer-aided design (CAD) techniques. Using an interactive, designer-controlled approach with automated source code transformations, our computer-aided recoding technique derives an executable parallel system model directly from available sequential reference code. Specifically, we describe three sets of source code transformations that create structural hierarchy, expose potential parallelism, and create explicit communication and synchronization. As a result, system modeling is significantly streamlined. Our experimental results demonstrate the shortened design time and higher productivity.
Slides

8D-2 (Time: 10:55 - 11:20)
Title(Invited Paper) TLM Automation for Multi-core Design
Author*Samar Abdi (Concordia University, Canada)
Pagepp. 717 - 724
Keywordtransaction level modeling, multi-core design, embedded systems
AbstractTransaction Level Models (TLMs) are being increasingly used by multi-core system designers for design validation and embedded SW development. However, with well defined modeling semantics and TLM automation tools, it is also possible to use TLMs for multi-core design. This paper presents recent research in automatic generation of timed TLMs for early, yet reliable, evaluation of multi-core design decisions. The TLMs are automatically generated from a given mapping of a concurrent application to a multi-core platform. The application code is annotated with delays at the basic-block level of granularity. Similarly, the platform services, such as communication and scheduling, also include timing delays. The TLM automation methods have been implemented in the Embedded System Environment (ESE) toolset. Our experimental results with ESE demonstrate that multi-core TLMs can be generated in the order of seconds; they simulate close to host-compiled application execution speed, and are more than 90% accurate compared to board measurements on average for industrial size examples. Therefore, TLM automation enables early and reliable evaluation of multi-core design decisions.
Slides

8D-3 (Time: 11:20 - 11:45)
Title(Invited Paper) Platform Modeling for Exploration and Synthesis
Author*Andreas Gerstlauer (University of Texas, Austin, U.S.A.), Gunar Schirner (Northeastern University, Boston, U.S.A.)
Pagepp. 725 - 731
KeywordSystem-level design, Modeling, TLM, ESL
AbstractEver increasing complexity and heterogeneity of system platforms drive the need for a move to higher levels of abstraction accompanied by corresponding design automation tools. The basis for any automated flow are well-defined design models. In this paper, we present an overview and taxonomy of platform modeling at various levels. Experiments demonstrate the benefits of fast yet accurate intermediate models at varying levels for rapid, early design space exploration. Furthermore, paired with automatic model generation and hardware/software synthesis, an automated path from specification to implementation becomes possible
Slides

8D-4 (Time: 11:45 - 12:10)
Title(Invited Paper) Application of ESL Synthesis on GSM Edge Algorithm for Base Station
Author*Alan P. Su (Global Unichip, Taiwan)
Pagepp. 732 - 737
KeywordESL, ESL Synthesis, hardware-software codesign, hardware-software partitioning, Genetic Algorithm
AbstractElectronic System Level (ESL) design methodology has been widely adopted in SoC designing, especially for designs with multiple cores. High level synthesis is now becoming a standard tool in the ESL design flow. People use the term ESL Synthesis to suggest the solution for multicore system synthesis. In this paper we argue that ESL Synthesis is architecture synthesis, high level synthesis and software synthesis combined. A multicore architecture synthesis algorithm had been implemented and proven in an experimental industry use. We successfully synthesized the target application, a GSM Edge algorithm for base station, into single and multicore systems. With this experience we developed the theory how high level synthesis and software synthesis should work with architecture synthesis to perform the task of ESL synthesis. Possible future research directions inspired by this work are also proposed. Key contributions of this work are (1) a user-defined cost function mechanism, (2) a warranted convergence mechanism and (3) combine above two mechanisms to waive the need for a universal cost function.
Slides