| Title | Parametric Yield Driven Resource Binding in Behavioral Synthesis with Multi-Vth/Vdd Library |
| Author | *Yibo Chen (Penn State University, U.S.A.), Yu Wang (Tsinghua University, China), Yuan Xie (Penn State University, U.S.A.), Andres Takach (Mentor Graphics Corporation, U.S.A.) |
| Page | pp. 781 - 786 |
| Keyword | high-level synthesis, parametric yield |
| Abstract | The ever-increasing chip power dissipation in SoCs has imposed great challenges on today's circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vdd optimizations are performed under deterministic conditions. With the increasing process variability that has significant impact on both the power dissipation and performance of circuit designs, it is necessary to employ statistical approaches in analysis and optimizations for low power. This paper studies the impact of process variations on the multi-Vth/Vdd technique at the behavioral synthesis level. A multi-Vth/Vdd resource library is characterized for delay and power variations at different voltage combinations. A parametric yield-driven resource binding algorithm is then proposed, which uses the characterized power and delay distributions and efficiently maximizes power yield under a timing yield constraint. During the resource binding process, voltage level converters are inserted between resources when required. Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worst-case based deterministic approaches. |
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| Title | Optimizing Blocks in an SoC Using Symbolic Code-Statement Reachability Analysis |
| Author | *Hong-Zu Chou (National Taiwan University, Taiwan), Kai-Hui Chang (Avery Design Systems, U.S.A.), Sy-Yen Kuo (National Taiwan University, Taiwan) |
| Page | pp. 787 - 792 |
| Keyword | RTL symbolic simulation, Reachability, Synthesis, Optimization |
| Abstract | Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused design blocks. In this paper, we propose techniques and methodologies that utilize abundant external don’t-cares that exist in an SoC environment for block optimization. Our symbolic code-statement reachability analysis can extract don’t-care conditions from constrained-random testbenches or other design blocks to identify unreachable conditional blocks in the design code. Those blocks can then be removed before logic synthesis is performed to produce smaller and more power-efficient final circuits. Our results show that we can optimize designs under different constraints and provide additional flexibility for SoC design flows. |
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| Title | High Level Event Driven Thermal Estimation for Thermal Aware Task Allocation and Scheduling |
| Author | *Jin Cui, Douglas L. Maskell (Nanyang Technological University, Singapore) |
| Page | pp. 793 - 798 |
| Keyword | Thermal-Aware Scheduling, Event Driven, High Level Estimation |
| Abstract | Thermal aware scheduling(TAS) is an important system level optimization for CMP and MPSoC. An event driven thermal estimation method which can assist dynamic TAS is proposed in this paper. The event driven thermal estimation is based upon a thermal map which is updated only when a high level event occurs. To minimize the overhead, while maintaining the estimation accuracy, the prebuilt look-up-tables and the superposition principle are used to speed up the solution of the thermal RC network. Experimental results show our method is accurate, producing thermal estimations of similar quality to existing thermal simulators,while having a considerably reduced computational complexity. Our event driven thermal estimation technique is significantly better, in terms of accuracy, than existing TAS schedulers, making it highly suitable for integration into the OS kernel. |
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| Title | Mapping and Scheduling of Parallel C Applications with Ant Colony Optimization onto Heterogeneous Reconfigurable MPSoCs |
| Author | Fabrizio Ferrandi, *Christian Pilato, Donatella Sciuto, Antonino Tumeo (Politecnico di Milano, Italy) |
| Page | pp. 799 - 804 |
| Keyword | MPSoC, Ant Colony Optimization, scheduling, mapping |
| Abstract | Efficient mapping and scheduling of partitioned applications are crucial to improve the performance on today reconfigurable multiprocessor systems-on-chip (MPSoCs) platforms. Most of existing heuristics adopt the Directed Acyclic (task) Graph as representation, that unfortunately, is not able to represent typical embedded applications (e.g., real-time and loop-partitioned). In this paper we propose a novel approach, based on Ant Colony Optimization, that explores different alternative designs to determine an efficient hardware-software partitioning, to decide the task allocation and to establish the execution order of the tasks, dealing with different design constraints imposed by a reconfigurable heterogeneous MPSoC. Moreover, it can be applied to any parallel C application, represented through Hierarchical Task Graphs. We show that our methodology, addressing a realistic target architecture, outperforms existing approaches on a representative set of embedded applications. |
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