Archive
Program at a glance
Keynote addresses
- Keynote I: Non-Volatile Memory and Normally-Off Computing
Takayuki Kawahara (Hitachi, Japan) - Keynote II: Managing Increasing Complexity through Higher-Level of Abstraction: What the Past Has Taught Us about the Future
WAjoy Bose (Atrenta Inc., U.S.A.) - Keynote III: Robust Systems: From Clouds to Nanotubes
Subhasish Mitra (Stanford Univ., U.S.A.)
Special sessions
- 2D: Emerging Memory Technologies and Its Implication on Circuit Design and Architectures
- 3C: Post-Silicon Techniques to Counter Process and Electrical Parameter Variability
- 3D: Recent Advances in Verification and Debug
- 4D: Advanced Patterning and DFM for Nanolithography beyond 22nm
- 7D: Virtualization, Programming, and Energy-Efficiency Design Issues of Embedded Systems
Designers' Forum
- 5D: C-P-B Co-design/Co-verification Technology for DDR3 1.6G in Consumer Products
- 6D: Emerging Technologies for Wellness Applications
- 8D: State-of-The-Art SoCs and Design Methodologies
- 9D: Advanced Packaging and 3D Technologies
University LSI Design Contest
Technical Sessions
- 1A: Analog, Mixed-Signal & RF Verification, Abstraction and Analysis
- 1B: Emerging Memories and System Applications
- 1C: Advances in Model Order Reduction and Extraction Techniques
- 2A: Scheduling Techniques for Embedded Systems
- 2B: Memory Architecture and Buffer Optimization
- 2C: Modeling for Signal and Power Integrity
- 3A: High-Level Embedded Systems Design Techniques
- 3B: Timing, Power, and Thermal Issues
- 4A: Design Automation for Emerging Technologies
- 4B: Novel Network-on-Chip Architecture Design
- 4C: Architecture Design and Reliability
- 5A: System-Level Simulation
- 5B: Resilient and Thermal-Aware NoC Design
- 5C: High-Level and Logic Synthesis
- 6A: Design Validation Techniques
- 6B: Clock Network Design
- 6B: Advances in Routing
- 7A: System Level Analysis and Optimization
- 7B: NBTI and Power Gating
- 7C: Physical Design for Yield
- 8A: Modeling and Design for Variability
- 8B: Test for Reliability and Yield
- 8C: System-Level Power Optimization
- 9A: Printability and Mask Optimization
- 9B: Emerging Solutions in Scan Testing
- 9C: Clock and Package