Title | Template-based Memory Access Engine for Accelerators in SoCs |
Author | *Bin Li, Zhen Fang, Ravi Iyer (Intel Corp., U.S.A.) |
Page | pp. 147 - 153 |
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Title | Realization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems |
Author | *Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch (Royal Inst. of Tech., Sweden) |
Page | pp. 154 - 159 |
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Slides |
Title | Network-on-Chip Router Design with Buffer-Stealing |
Author | Wan-Ting Su, *Jih-Sheng Shen, Pao-Ann Hsiung (National Chung Cheng Univ., Taiwan) |
Page | pp. 160 - 164 |
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Slides |
Title | Minimizing Buffer Requirements for Throughput Constrained Parallel Execution of Synchronous Dataflow Graph |
Author | Tae-ho Shin (Seoul National Univ., Republic of Korea), Hyunok Oh (Hanyang Univ., Republic of Korea), *Soonhoi Ha (Seoul National Univ., Republic of Korea) |
Page | pp. 165 - 170 |
Detailed information (abstract, keywords, etc) | |
Slides |