| Title | (Invited Paper) Post-silicon Bug Detection for Variation Induced Electrical Bugs |
| Author | Ming Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng (University of California, Santa Barbara, U.S.A.) |
| Page | pp. 273 - 278 |
| Abstract | Electrical bugs, such as those caused by crosstalk or power droop, are a growing concern due to shrinking noise margins and increasing variability. This paper introduces COBE, an electrical bug modeling technique which can be used to evaluate the effectiveness of validation tests and DfD (design-for-debug) structures for detecting these errors in post-silicon validation. COBE first uses gate-level timing details to identify critical flip-flops in which the error effects of electrical bugs are more likely to be captured. Based on RTL simulation traces, the functional tests and corresponding cycles in which these critical flip-flops incur transitions are then recorded as the potential times and locations of bug activation. These selected “bit-flips” are then analyzed through functional simulation to determine if they are propagated to an observation point for detection. Compared to the commonly employed random bit-flip injection technique, COBE provides a significantly more accurate electrical bug model by taking into account the likelihood of bug activation, in terms of both location and time, for bit-flip injection. COBE is experimentally evaluated on an Alpha 21264 processor RTL model. In our simulation-based experiments, the results show that the relative effectiveness of the tests predicted by COBE correlates very well with the tests' electrical bug detection capability, with a correlation factor of 0.921. This method is much more accurate than the random bit-flip injection technique, which has a correlation factor of 0.482. |
| Title | (Invited Paper) Diagnosis-assisted Supply Voltage Configuration to Increase Performance Yield of Cell-Based Designs |
| Author | Jing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu (National Tsing Hua University, Taiwan) |
| Page | pp. 279 - 284 |
| Abstract | A diagnosis technique based on delay testing has been developed to map the severity of process variation on each cell/interconnect delay. Given this information, we demonstrate a post-silicon tuning method on row voltage supplies (inside a chip) to restore the performance of failed chips. The method uses the performance map to set voltages by either pumping up the voltage on cells with worse delays or tuning down on fast cells to save power. On our test cases, we can correct up to 75%of failed chips to pass performance tests, while maintaining less than 10% increase over nominal power consumption. |
| Title | (Invited Paper) Run-Time Adaptive Performance Compensation using On-chip Sensors |
| Author | Masanori Hashimoto (Osaka University & JST, CREST, Japan) |
| Page | pp. 285 - 290 |
| Abstract | This paper discusses run-time adaptive performance control with on-chip sensors that predict timing errors. The sensors embedded into functional circuits capture delay variations due to not only die-to-die process variation but also random process variation, environmental fluctuation and aging. By compensating circuit performance according to the sensor outputs, we can overcome PVT worst-case design and reduce power dissipation while satisfying circuit performance. We applied the adaptive speed control to subthreshold circuits that are very sensitive to random variation and environmental fluctuation. Measurement results of a 65nm test chip show that the adaptive speed control can compensate PVT variations and improve energy efficiency by up to 46% compared to the worst-case design and operation with guardbanding. |
| Title | (Invited Paper) The Alarms Project: A Hardware/Software Approach to Addressing Parameter Variations |
| Author | David Brooks (Harvard University, U.S.A.) |
| Page | p. 291 |
| Abstract | Parameter variations (process, voltage, and temperature) threaten continued performance scaling of power-constrained computer systems. As designers seek to contain the power consumption of microprocessors through reductions in supply voltage and power-saving techniques such as clock-gating, these systems suffer increasingly large power supply fluctuations due to the finite impedance of the power supply network. These supply fluctuations, referred to as voltage emergencies, must be managed to guarantee correctness. Traditional approaches to address this problem incur high-cost or compromise power/performance efficiency. Our research seeks ways to handle these alarm conditions through a combined hardware/software approach, motivated by root cause analysis of voltage emergencies revealing that many of these events are heavily linked to both program control flow and microarchitectural events (cache misses and pipeline flushes). This talk will discuss three aspects of the project: (1) a fail-safe mechanism that provides hardware guaranteed correctness; (2) a voltage emergency predictor that leverages control flow and microarchitectural event information to predict voltage emergencies up to 16 cycles in advance; and (3) a proof-of-concept dynamic compiler implementation that demonstrates that dynamic code transformations can be used to eliminate voltage emergencies from the instruction stream with minimal impact on performance. |