Title | Area-Efficient FPGA Logic Elements: Architecture and Synthesis |
Author | *Jason Anderson (Univ. of Toronto, Canada), Qiang Wang (Xilinx, Inc., U.S.A.) |
Page | pp. 369 - 375 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Selectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance |
Author | *Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea) |
Page | pp. 376 - 381 |
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Slides |
Title | A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization |
Author | *Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan) |
Page | pp. 382 - 387 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | SETmap: A Soft Error Tolerant Mapping Algorithm for FPGA Designs with Low Power |
Author | Chi-Chen Peng, Chen Dong, *Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.) |
Page | pp. 388 - 393 |
Detailed information (abstract, keywords, etc) |