| Title | (Invited Paper) All-out Fight against Yield Losses by Design-manufacturing Collaboration in Nano-lithography Era |
| Author | Soichi Inoue, Sachiko Kobayashi (Toshiba, Japan) |
| Page | pp. 395 - 401 |
| Abstract | The concept of design-manufacturing collaboration for nano-lithography era has been clarified. The novel design-manufacturing system that the manufacturing tolerance reflecting design intention properly can be allocated to the layout has been proposed. According to the system, one can assign the “weak portion” explicitly on the layout, and can control the process for reducing the burden of manufacturing and further getting higher yield. More specifically, the extraction of electrically critical portion and conversion to the manufacturing tolerance has been demonstrated. The tolerance has applied to reduce computational burden of mask data preparation. Besides, the yield model-based layout scoring system has been also suggested to be significant remarkably. One can check the layout and modify not to loose the yield. Creation of yield function, layout scoring, and layout modification based upon the yield model have been demonstrated. |
| Title | (Invited Paper) EUV Lithography: Prospects and Challenges |
| Author | Sam Sivakumar (Intel Corporation, U.S.A.) |
| Page | p. 402 |
| Abstract | Integrated circuit scaling as codified in Moore’s Law has been enabled through the tremendous advances in lithographic patterning technology over multiple process generations. Optical lithography has been the mainstay of patterning technology to date. Its imminent demise has been oft proclaimed over the years but clever engineering has consistently been able to extend it through many lens size and wavelength changes. NA has increased steadily from about 0.3 to 1.35 today with improvements in lens design and the use of immersion lithography. Simultaneously, the illumination wavelength has been reduced from 436nm about 20 years ago to 193nm for state-of-the-art scanners today. However, this approach has reached its limits. The 22nm technology node, targeted for HVM in 2011, represents the last instance of using standard 1.35NA immersion lithography-based patterning for the critical layers with a k1 hovering right around the 0.3 value that is considered acceptable for manufacturability. For the 14nm node with a HVM date of 2013, one has to resort to double patterning to achieve a manufacturable k1. For the 10nm technology node with a 2015 HVM date, double patterning will also be insufficient. While further ArF extension schemes are being considered, the industry is working towards lowering the wavelength from 193nm to Extreme Ultraviolet Lithography with a λ of 13.5nm. EUV offers the prospect of operating at significantly higher k1 and as a consequence, much simpler design rules and potentially simpler OPC. However, the technical challenges are formidable. EUV lithography requires the re-engineering of every subsystem in the optical path - source, collector and projection optics, reticles and photoresists. A huge industry-wide effort is under way to solve these technical issues and bring 13.5nm EUV lithography to production. Two main approaches are being considered for EUV sources - Laser Produced Plasma (LPP) and Discharge Produced Plasma (DPP). Both approaches appear to be heading towards production and it remains to be seen if one approach is more scalable to higher power levels. Currently however, neither approach is close to the power levels required to deliver runrates that will have a reasonable Cost of Ownership (COO). Clearly, a lot of development is ahead to make this happen. Photoresists have also seen a significant amount of technical development, primarily using small field Micro Exposure Tools (MET). Photoresist companies are working on developing the chemical platforms needed for EUV photoresists. While much progress has been made on photospeed, resolution and linewidth roughness, further improvements are required to meet the needs of the 14nm and 10nm process nodes. Since EUV employs reflective optics, EUV reticles are reflective as well and this poses several challenges. Apart from the obvious complexities of EUV reticle manufacturing, defectivity is a major concern, both from the standpoint of making defect-free masks as well as from the requirement of detecting the defects and repairing them. A significant industry-wide effort is being driven both among individual companies and through consortia like SEMATECH to develop both the manufacturing techniques required to make high-quality masks and the inspection and repair capabilities needed. Probably the most complex technical challenge and one largely untested in an HVM sense is the scanner itself. The current state of the art is the ASML Alpha Demo Tool (ADT) currently in use at SEMATECH and IMEC. This 0.25NA tool has a low runrate and limited technical capabilities but can print full fields and has been a valuable tool in the early demonstration of integrated device and circuit fabrication using EUV lithography. Working SRAM cells and other circuits have been demonstrated with very promising results. The first development-quality EUV scanners are targeted to ship to end users in 2011, while the HVM versions with high targeted runrates and low targeted COO are slated for delivery beginning in mid-2012. The delivery of these tools at the end users’ fab and their subsequent integration into the process flow will pose the greatest challenge and is expected to require a significant outlay of engineering effort and resources in the next 2 years. EUV presents its own challenges in terms of non-idealities that would need to be quantified and corrected for. While conventional OPC may be minimal, EUV has other sources of variability including flare and mask shadowing that would need to be compensated for. Moreover, the likelihood of defects on EUV masks brings up the possibility of pattern shifting to place the defects in benign areas of the reticle. All of these new challenges require OPC, synthesis or other data manipulation methodologies to be developed for EUV. This paper will attempt to highlight the key technical challenges of EUV lithography and where the industry will need to focus its efforts over the next 2 years to make EUV manufacturing successful and cost-effective. |
| Title | (Invited Paper) Future Electron-Beam Lithography and Implications on Design and CAD Tools |
| Author | Jack J.H. Chen, Faruk Krecinic, Jen-Hom Chen, Raymond P.S. Chen, Burn J. Lin (Taiwan Semiconductor Manufacturing Company, Taiwan) |
| Page | pp. 403 - 404 |
| Abstract | The steeply increasing price and difficulty of masks make the mask-based optical lithography, such as ArF immersion lithography and extreme ultra-violet lithography (EUVL), unaffordable when going beyond the 32-nm half-pitch (HP) node[1]. Electron beam direct writing (EBDW), so called maskless lithography (ML2), provides an ultimate resolution without jeopardy from masks, but the extremely low productivity of the traditional single beam systems made it very laborious for mass manufacturing after over 3 decades of development. Although electron beam lithography has been long used for mask writing, it is yet very slow and typically takes from hours to days to write a complete 6-inch high-end mask. Direct writing a 300-mm wafer definitely would take much longer. Considering production efficiency in the cleanroom, the throughput of lithography tools should be in the order of 10 wafers per hour (WPH) per square meter as compared to that of an ArF scanner. To achieve such a throughput per e-beam column requires an improvement of more than 3-order. Increasing the beam current in the conventional single beam system would induce the space charge effect and thus is not a solution. Several groups [2][3][4][5] have proposed different multiple electron beam maskless lithography (MEBML2) approaches, by multiplying either Gaussian beams, variable shape beams or by using cell projections, to increase the throughput. The maturing MEMS technology and electronic control technology enable precise control of more than ten thousands or even millions of electron beamlets, writing in parallel. Without the mask constraint, the exposure can be made by continuously scanning across the entire wafer diameter as long as the ultra-high speed data rate can be supported. Hence a much slower scan speed is required and therefore a small tool footprint is achievable. A MAPPER Pre-Alpha Tool, composed of a 110-beam 5-keV column and a 300-mm wafer stage within a vacuum chamber of 1.3x1.3m2 footprint, has been installed and operational for process development in the advanced Giga-Fab cleanroom environment. By sending the pre-treated optical data to the correspondent photodiode of each blanker, each beam writes its own features independently in raster scan mode. Resolution beyond 30-nm HP resolution for both C/H and L/S by using chemical amplified resist (CAR) has been demonstrated. Applying proper E-beam proximity corrections (EPC), a 20-nm node test circuit layout has been successfully patterned. The tool will be upgraded with a new Electron-Optics column containing 13,000 beamlets and each beamlet projecting 7x7 sub-beams to achieve 10 WPH of 32-nm HP node wafers by a single chamber. The achievement of high productivity MEBML2 needs not only the beams, but also the data preparation. For a 10-WPH MEBML2 tool, one wafer exposure is done in 6 minutes. However, the pre-treatments, for example logic operation and EPC, of the huge reticle field data file typically take a few days in present-day mask writing and therefore drastic speed enhancement is required to really gain the benefits of ML2 in cycle time and flexibility. In MAPPER’s writing approach, the circuit layout in GDSII or OASIS format at sub-nm addressing grid, whose file size can be up to hundreds of Giga-Bytes after EPC, has to be pre-rasterized to a bitmap writing format of 3.5-nm grid, which file size of the simple 0 and 1 bitmap for a full-26mmx33mm reticle field becomes more than 10 Tera-Bytes(TB). Real-time data decompression in the data path of the tool is designed to avoid storage and transportation of the extremely huge files. In this presentation, several suggestions regarding design, EPC and CAD tools to best fit the nature and operation of MEBML2 in high volume manufacturing are made. Because of high resolution by the e-beam, the restricted design rules due to resolution limit of the optical lithography, especially those related to the double patterning techniques, can be removed. By considering the speed of data treatment, required storage, and computing resources inside the data path, some minor rules like on-pixel design may be recommended. Although contour-based EPC has been demonstrated to meet CD requirements [6][7], hybrid EPC accompanied with dose modulation has been proposed to further enhance the imaging contrast. Even though we will optimize the tool precision to eliminate most of the beam-to-beam CD and overlay errors, it is nevertheless safer to propose some methods to avoid the BtB stitching on critical devices. |
| Title | (Invited Paper) Exploration of VLSI CAD Researches for Early Design Rule Evaluation |
| Author | Chul-Hong Park (Samsung Electronics, Republic of Korea), David Z. Pan (University of Texas at Austin, U.S.A.), Kevin Lucas (Synopsys, U.S.A.) |
| Page | pp. 405 - 406 |
| Abstract | Design rule has been a primary metric to link design and technology, and is likely to be considered as IC manufacturer’s role for the generation due to the empirical and unsystematic in nature. Disruptive and radical changes in terms of layout style, lithography and device in the next decade require the design rule evaluation in early development stage. In this paper, we explore VLSI CAD researches for early and systematic evaluation of design rule, which will be a key technique for enhancing the competitiveness in IC market. |