第16回アジア南太平洋設計自動化会議 (ASP-DAC 2011）

日程: 2011年1月25日（火）～28日（金）
場所: パシフィコ横浜, 横浜市



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特別セッション

• Date: January 26 - 28, 2011
• Place: Pacifico Yokohama, Conference Center, 4F

1D : Wednesday, January 26, 10:15-12:20

Presentation + Poster Discussion: "University LSI Design Contest"

2D : Wednesday, January 26, 13:30-15:35

Invited Talks: "Emerging Memory Technologies and Its Implication on Circuit Design and Architectures"

Organizer: Yuan Xie (Pennsylvania State University, USA)

Speakers:

• Meng-Fan (Marvin) Chang (National Tsing Hua University, Taiwan)
• Yiran Chen and Hai Li (University of Pittsburgh and New York University, USA) Syed M. Alam (Everspin Technologies, Inc., USA)
• Yuan Xie (Pennsylvania State University, USA)

Abstract: "The performance and power for non-volatile memory have been consistently improved; the density has been improved and the cost has dropped dramatically as fabrication has become more efficient and the market has grown. New types of non-volatile memory, such as Phase Change RAM (PCRAM) , Magnetic RAM (MRAM), Resistive RAM (RRAM), and Memristor-based Memory, attract many interests in both academia and industry. This special session consists of four invited talks, giving introductions and discussions on a variety of promising emerging memory technologies.

3D : Wednesday, January 26, 15:55-18:00

Invited Talks: "Recent Advances in Verification and Debug"

Organizer: Chung-Yang (Ric) Huang (National Taiwan University, Taiwan)

Speakers:

• Miroslav Velev (Aries Design Automation, USA) on “Automatic Formal Verification of Reconfigurable DSPs”
• Chung-Yang (Ric) Huang (National Taiwan University, Taiwan) on “SoC HW/SW Co-simulation and Validation”
• Masahiro Fujita (Univ. Tokyo, Japan) on “Utilizing high level design information to speed up post-silicon debugging”
• Andreas Veneris (Univ. Toronto, Canada) on “From RTL to Silicon: The Case for Debug Automation”

Abstract: "In the modern design cycle, verification has been found to be the biggest bottleneck consuming as much as 70% of the overall chip development time. Half of this time is spent on debugging a design that fails verification. Further, the verification pain today is felt all the way down to the silicon, as design errors propagate to chip prototypes and can jeopardize the tight time-to-market product deadlines. In this special session, we will present several recent advances in verification and debugging. We will start by demonstrating how formal verification can be automatically applied to a reconfigurable VLIW processor prototype. This processor is binary-code compatible with the PowerPC 750 Instruction Set Architecture (ISA) and is optimized for space communications in future space missions of NASA. We will next present a HW/SW co-simulation and validation framework that combines a software development environment and one or more FPGA boards through the SCE-MI interface. By simulating the design in transaction-level modeling (TLM) and instrumenting the FPGA netlist with an embedded vector processor interface (eVPI), the framework can achieve million-instruction-per-second simulation speed as well as a full signal visibility for FPGA debugging. The second half of the session will include two talks on enhancing well-needed debugging capabilities. The first one will present a methodology for utilizing high-level design information to speed up post-silicon debugging based on an incremental high-level synthesis technique. The second will conclude the session by discussing debug automation. While up-to-date debugging methodologies all heavily rely on human efforts, the talk will address the need for good automated debugging methodologies at a high level, the use of SVA to increase coverage, techniques for debug at the RTL, and impact on silicon debug today. The session will close with a short interaction with the audience, allowing them to ask questions.

4D : Thursday, January 27, 10:15-12:20

Invited Talks: "Advanced Patterning and DFM for Nanolithography beyond 22nm"

Organizer: David Z. Pan (Univ. of Texas at Austin, USA) and Kevin Lucas (Synopsys, USA)

Speakers:

• Soichi Inoue (Toshiba, Japan)
• Sam Sivakumar (Intel, USA)
• Jack Chen (TSMC, USA)
• Chul-Hong Park (Samsung, Korea)

Abstract: "This special session features four invited talks from leading semiconductor companies on advanced patterning and DFM for nanolithography beyond 22nm. As 193nm immersion lithography with single exposure is reaching its physical limit, double patterning lithography is perceived as a leading candidate for 22nm/15nm nodes. Meanwhile, extreme ultra violet (EUV) lithography and maskless lithography such as multiple e-beam direct writes are under heavy research and development. These talks will cover key future nanolithography candidates and discuss their challenges/opportunities on nanometer IC design and CAD tools.

3C : Wednesday, January 26, 15:55-18:00

Invited Talks: " Post-Silicon Techniques to Counter Process and Electrical Parameter Variability"

Organizer: Jing-Jia Liou (National Tsing Hua University, Taiwan)

Speakers:

• Tim Cheng (UCSB, USA)
• Jing-Jia Liou (National Tsing Hua University, Taiwan)
• Masanori Hashimoto (Osaka University, Japan)
• David Brooks (Harvard University, USA)

Abstract: "Variability has become an inherent part of the design process. Either process variations or electrical parameter fluctuations (voltage, temperature, etc.) present challenging tasks for designers. While large body of techniques have been developed to guardband variability, greater probabilities of escaped detection or mis-prediction are likely to be found after tapeout. This special session explores modeling, discovering and coping with variations at post-silicon stage with four informational talks. The first talk will discuss electrical bug modeling, and the development of coverage metrics for quality evaluation of post-silicon validation tests for detecting electrical bugs, which is an essential link to reflect the root problems of a design. At the second talk, we introduce a test data analysis method to uncover the location of larger process variations and tune on-chip voltage regulators to counter the variations while keeping power envelope under specification. In the third talk, we introduce the on-line sensing techniques to detect variations and use this knowledge in design to proactively eliminate the effects from variations. And finally, we will discuss several techniques to handle electrical fluctuations through a combined hardware/software approach at micro-architectural levels.

7D : Friday, January 28, 10:15-12:20

Invited Talks: "Virtualization, Programming, and Energy-Efficiency Design Issues of Embedded Systems"

Organizer: Tei-Wei Kuo (National Taiwan University, Taiwan)

Speakers:

• Tatsuo Nakajima (Waseda University, Japan)
• Patrick H. Madden ( SUNY Binghamton, USA)
• Jen-Wei Hsieh (National Taiwan University of Science and Technology, Taiwan)
• Tei-Wei Kuo (National Taiwan University, Taiwan)

Abstract: "The designs of embedded systems are complicated with quick platform evolving and overloading of user applications in recent years. Many embedded systems are now built up over platforms of multiple cores and even consider the concept of virtual cores. Energy consumption also becomes extremely critical in virtually all aspects in system designs. In this special session, four invited talks will address design issues related to programming in multi-core environments, virtualization, and energy efficient designs.

Last Updated on: 11, 15, 2010