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The 17th Asia and South Pacific Design Automation Conference

Session 1C  Emerging Circuits and Memories
Time: 14:00 - 15:40 Tuesday, January 31, 2012
Location: Room 202
Chairs: Yiran Chen (Univ. of Pittsburgh, U.S.A.), Hai Zhou (Northwestern Univ., U.S.A.)

1C-1 (Time: 14:00 - 14:25)
TitleAn ILP-based Obstacle-Avoiding Routing Algorithm for Pin-Constrained EWOD Chips
Author*Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Pagepp. 67 - 72
Detailed information (abstract, keywords, etc)

1C-2 (Time: 14:25 - 14:50)
TitleA Look Up Table Design with 3D Bipolar RRAMs
AuthorYi-Chung Chen (Polytechnic Inst. of New York Univ., U.S.A.), *Wei Zhang (Nanyang Technological Univ., Singapore), Hai Li (Polytechnic Inst. of New York Univ., U.S.A.)
Pagepp. 73 - 78
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1C-3 (Time: 14:50 - 15:15)
TitleLow Power Memristor-Based ReRAM Design with Error Correcting Code
Author*Dimin Niu, Yang Xiao, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Pagepp. 79 - 84
Detailed information (abstract, keywords, etc)

1C-4 (Time: 15:15 - 15:40)
TitleSynthesis of Reversible Circuits with Minimal Lines for Large Functions
AuthorMathias Soeken, *Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler (Univ. of Bremen, Germany)
Pagepp. 85 - 92
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