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The 17th Asia and South Pacific Design Automation Conference

Session 2A  System-Level Optimization Techniques for Multi-Core Architectures
Time: 16:10 - 17:50 Tuesday, January 31, 2012
Location: Room 204B
Chairs: Kiyoung Choi (Seoul National Univ., Republic of Korea), Yuko Hara-Azumi (Ritsumeikan Univ., Japan)

2A-1 (Time: 16:10 - 16:35)
TitleLearning-Based Power Management for Multi-Core Processors via Idle Period Manipulation
AuthorRong Ye, *Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 115 - 120
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2A-2 (Time: 16:35 - 17:00)
TitleMemory Access Aware Power Gating for MPSoCs
Author*Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang (National Taiwan Univ., Taiwan), Naehyuck Chang (Seoul National Univ., Republic of Korea)
Pagepp. 121 - 126
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2A-3 (Time: 17:00 - 17:25)
TitleBuffer Minimization in Pipelined SDF Scheduling on Multi-Core Platforms
AuthorYuankai Chen, *Hai Zhou (Northwestern Univ., U.S.A.)
Pagepp. 127 - 132
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2A-4 (Time: 17:25 - 17:50)
TitleA Hierarchical C2RTL Framework for FIFO-Connected Stream Applications
Author*Shuangchen Li, Yongpan Liu, Daming Zhang, Xinyu He (Tsinghua Univ., China), Pei Zhang (Y Explorations Inc., U.S.A.), Huazhong Yang (Tsinghua Univ., China)
Pagepp. 133 - 138
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