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The 17th Asia and South Pacific Design Automation Conference

Session 2C  Emerging Test Solutions
Time: 16:10 - 17:50 Tuesday, January 31, 2012
Location: Room 202
Chairs: Jiun-Lang Huang (National Taiwan Univ., Taiwan), Wu-Tung Cheng (Mentor Graphics, U.S.A.)

2C-1 (Time: 16:10 - 16:35)
TitleAn Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
AuthorChia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, *Charles H.-P. Wen (National Chiao Tung Univ., Taiwan), Jayanta Bhadra (Freescale Semiconductor Inc., U.S.A.)
Pagepp. 163 - 168
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2C-2 (Time: 16:35 - 17:00)
TitleCODA: A Concurrent Online Delay Measurement Architecture for Critical Paths
AuthorYubin Zhang (Chinese Academy of Sciences, China), Haile Yu, *Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 169 - 174
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2C-3 (Time: 17:00 - 17:25)
TitleLow-cost Control Flow Error Protection by Exploiting Available Redundancies in the Pipeline
AuthorMohammad Abdur Rouf, *Soontae Kim (KAIST, Republic of Korea)
Pagepp. 175 - 180
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2C-4 (Time: 17:25 - 17:50)
TitleDetection and Diagnosis of Faulty Quantum Circuits
Author*Alexandru Paler, Ilia Polian (Univ. of Passau, Germany), John P. Hayes (Univ. of Michigan, U.S.A.)
Pagepp. 181 - 186
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