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The 17th Asia and South Pacific Design Automation Conference

Session 3B  High-Level Synthesis
Time: 10:40 - 12:20 Wednesday, February 1, 2012
Location: Room 203
Chairs: Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan)

3B-1 (Time: 10:40 - 11:05)
TitlePerformance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range
Author*Keisuke Inoue, Mineo Kaneko (JAIST, Japan)
Pagepp. 239 - 244
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3B-2 (Time: 11:05 - 11:30)
TitleClock Period Minimization with Minimum Area Overhead in High-Level Synthesis of Nonzero Clock Skew Circuits
Author*Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan)
Pagepp. 245 - 250
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3B-3 (Time: 11:30 - 11:55)
TitleClock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis
Author*Yuko Hara-Azumi, Hiroyuki Tomiyama (Ritsumeikan Univ., Japan)
Pagepp. 251 - 256
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3B-4 (Time: 11:55 - 12:20)
TitleAn Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis
Author*Yuxin Wang (Peking Univ. and UCLA/PKU Joint Research Inst. in Science and Engineering, China), Peng Zhang (Univ. of California, Los Angeles, U.S.A.), Xu Cheng (Peking Univ., China), Jason Cong (Univ. of California, Los Angeles and UCLA/PKU Joint Research Inst. in Science and Engineering, U.S.A.)
Pagepp. 257 - 262
Detailed information (abstract, keywords, etc)