Title | Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range |
Author | *Keisuke Inoue, Mineo Kaneko (JAIST, Japan) |
Page | pp. 239 - 244 |
Detailed information (abstract, keywords, etc) |
Title | Clock Period Minimization with Minimum Area Overhead in High-Level Synthesis of Nonzero Clock Skew Circuits |
Author | *Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan) |
Page | pp. 245 - 250 |
Detailed information (abstract, keywords, etc) |
Title | Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis |
Author | *Yuko Hara-Azumi, Hiroyuki Tomiyama (Ritsumeikan Univ., Japan) |
Page | pp. 251 - 256 |
Detailed information (abstract, keywords, etc) |
Title | An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis |
Author | *Yuxin Wang (Peking Univ. and UCLA/PKU Joint Research Inst. in Science and Engineering, China), Peng Zhang (Univ. of California, Los Angeles, U.S.A.), Xu Cheng (Peking Univ., China), Jason Cong (Univ. of California, Los Angeles and UCLA/PKU Joint Research Inst. in Science and Engineering, U.S.A.) |
Page | pp. 257 - 262 |
Detailed information (abstract, keywords, etc) |