Title | Block-level 3D IC Design with Through-Silicon-Via Planning |
Author | Dae Hyun Kim (Georgia Tech, U.S.A.), Rasit Onur Topaloglu (GLOBALFOUNDRIES, U.S.A.), *Sung Kyu Lim (Georgia Tech, U.S.A.) |
Page | pp. 335 - 340 |
Detailed information (abstract, keywords, etc) |
Title | Micro-Bump Assignment for 3D ICs using Order Relation |
Author | Ta-Yu Kuan, Yi-Chun Chang, *Tai-Chen Chen (National Central Univ., Taiwan) |
Page | pp. 341 - 346 |
Detailed information (abstract, keywords, etc) |
Title | Through-Silicon-Via-Induced Obstacle-Aware Clock Tree Synthesis for 3D ICs |
Author | Xin Zhao, *Sung Kyu Lim (Georgia Tech, U.S.A.) |
Page | pp. 347 - 352 |
Detailed information (abstract, keywords, etc) |
Title | Parallel Implementation of R-trees on the GPU |
Author | Lijuan Luo (Univ. of Illinois, Urbana-Champaign/NVIDIA Corp., U.S.A.), *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Lance Leong (NVIDIA Corp., U.S.A.) |
Page | pp. 353 - 358 |
Detailed information (abstract, keywords, etc) |