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The 17th Asia and South Pacific Design Automation Conference

Session 4B  3D IC Layout
Time: 14:00 - 15:40 Wednesday, February 1, 2012
Location: Room 203
Chairs: Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Yih-Lang Li (National Chiao Tung Univ., Taiwan)

4B-1 (Time: 14:00 - 14:25)
TitleBlock-level 3D IC Design with Through-Silicon-Via Planning
AuthorDae Hyun Kim (Georgia Tech, U.S.A.), Rasit Onur Topaloglu (GLOBALFOUNDRIES, U.S.A.), *Sung Kyu Lim (Georgia Tech, U.S.A.)
Pagepp. 335 - 340
Detailed information (abstract, keywords, etc)

4B-2 (Time: 14:25 - 14:50)
TitleMicro-Bump Assignment for 3D ICs using Order Relation
AuthorTa-Yu Kuan, Yi-Chun Chang, *Tai-Chen Chen (National Central Univ., Taiwan)
Pagepp. 341 - 346
Detailed information (abstract, keywords, etc)

4B-3 (Time: 14:50 - 15:15)
TitleThrough-Silicon-Via-Induced Obstacle-Aware Clock Tree Synthesis for 3D ICs
AuthorXin Zhao, *Sung Kyu Lim (Georgia Tech, U.S.A.)
Pagepp. 347 - 352
Detailed information (abstract, keywords, etc)

4B-4 (Time: 15:15 - 15:40)
TitleParallel Implementation of R-trees on the GPU
AuthorLijuan Luo (Univ. of Illinois, Urbana-Champaign/NVIDIA Corp., U.S.A.), *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Lance Leong (NVIDIA Corp., U.S.A.)
Pagepp. 353 - 358
Detailed information (abstract, keywords, etc)