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The 17th Asia and South Pacific Design Automation Conference

Session 4C  Simulation and Modeling for Signal-Integrity Analysis
Time: 14:00 - 15:40 Wednesday, February 1, 2012
Location: Room 202
Chairs: Rung-Bin Lin (Yuan Ze Univ., Taiwan), Youngsoo Shin (KAIST, Republic of Korea)

4C-1 (Time: 14:00 - 14:25)
TitleAn Adaptive LU Factorization Algorithm for Parallel Circuit Simulation
Author*Xiaoming Chen, Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Pagepp. 359 - 364
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4C-2 (Time: 14:25 - 14:50)
TitlePredictor-Corrector Latency Insertion Method for Fast Transient Analysis of Ill-Constructed Circuits
Author*Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ., Japan)
Pagepp. 365 - 370
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4C-3 (Time: 14:50 - 15:15)
TitleCrosstalk-Aware Statistical Interconnect Delay Calculation
Author*Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs (Delft Univ. of Tech., Netherlands)
Pagepp. 371 - 376
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4C-4 (Time: 15:15 - 15:40)
TitleFast Floating Random Walk Algorithm for Multi-Dielectric Capacitance Extraction with Numerical Characterization of Green's Functions
AuthorHao Zhuang (Tsinghua Univ./Peking Univ., China), *Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye (Tsinghua Univ., China)
Pagepp. 377 - 382
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