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The 17th Asia and South Pacific Design Automation Conference

Session 5B  Physical Optimization for Power and Timing
Time: 16:10 - 17:50 Wednesday, February 1, 2012
Location: Room 203
Chairs: Sheqin Dong (Tsinghua Univ., China), Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)

5B-1 (Time: 16:10 - 16:35)
TitleA Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function
AuthorSuradeth Aroonsantidecha, *Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 425 - 430
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5B-2 (Time: 16:35 - 17:00)
TitleCrosstalk-Aware Power Optimization with Multi-Bit Flip-Flops
Author*Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan)
Pagepp. 431 - 436
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5B-3 (Time: 17:00 - 17:25)
TitleTopology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization
Author*Yen-Hung Lin, Yun-Jian Lo, Jian-Syun Tong, Wen-Hao Liu, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 437 - 442
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5B-4 (Time: 17:25 - 17:50)
TitleVoltage Island-Driven Floorplanning Considering Level Shifter Placement
AuthorRichard C.J. Hsu, Wei-Yi Cheng, Chung-Lin Lee, *Jai-Ming Lin (National Cheng Kung Univ., Taiwan)
Pagepp. 443 - 448
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