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The 17th Asia and South Pacific Design Automation Conference

Session 6B  Circuit-Level Timing Optimization
Time: 8:30 - 10:10 Thursday, February 2, 2012
Location: Room 203
Chairs: Sachin Sapatnekar (Univ. of Minnesota, U.S.A.), Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)

6B-1 (Time: 8:30 - 8:55)
TitleA Semi-Formal Min-Cost Buffer Insertion Technique Considering Multi-Mode Multi-Corner Timing Constraints
Author*Shih Heng Tsai, Man Yu Li, Chung Yang Huang (National Taiwan Univ., Taiwan)
Pagepp. 505 - 510
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6B-2 (Time: 8:55 - 9:20)
TitleECO Timing Optimization with Negotiation-Based Re-Routing and Logic Re-Structuring Using Spare Cells
AuthorXing Wei, *Wai-Chung Tang, Yi Diao, Yu-Liang Wu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 511 - 516
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6B-3 (Time: 9:20 - 9:45)
TitleClock Rescheduling for Timing Engineering Change Orders
Author*Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang (National Taiwan Univ., Taiwan)
Pagepp. 517 - 522
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6B-4 (Time: 9:45 - 10:10)
TitleOptimal Prescribed-Domain Clock Skew Scheduling
AuthorLi Li, Yinghai Lu, *Hai Zhou (Northwestern Univ., U.S.A.)
Pagepp. 523 - 527
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