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The 17th Asia and South Pacific Design Automation Conference

Session 8B  Automated Debugging and Validation
Time: 14:00 - 15:40 Thursday, February 2, 2012
Location: Room 203
Chairs: Jiun-Lang Huang (National Taiwan Univ., Taiwan), Jai-Ming Lin (National Cheng Kung Univ., Taiwan)

8B-1 (Time: 14:00 - 14:25)
TitleA Formal Approach to Debug Polynomial Datapath Designs
Author*Bijan Alizadeh (Univ. of Tehran, Iran)
Pagepp. 683 - 688
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8B-2 (Time: 14:25 - 14:50)
TitleAutomated Debugging of Counterexamples in Formal Verification of Pipelined Microprocessors
Author*Miroslav N. Velev, Ping Gao (Aries Design Automation, U.S.A.)
Pagepp. 689 - 694
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8B-3 (Time: 14:50 - 15:15)
TitleOn Error Tolerance and Engineering Change with Partially Programmable Circuits
AuthorHratch Mangassarian (Univ. of Toronto, Canada), Hiroaki Yoshida (Univ. of Tokyo, Japan), Andreas Veneris (Univ. of Toronto, Canada), Shigeru Yamashita (Ritsumeikan Univ., Japan), *Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 695 - 700
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8B-4 (Time: 15:15 - 15:40)
TitleOn Error Modeling of Electrical Bugs for Post-Silicon Timing Validation
AuthorMing Gao, *Peter Lisherness (Univ. of California, Santa Barbara, U.S.A.), Jing-Jia Liou (National Tsing Hua Univ., Taiwan), Kwang-Ting (Tim) Cheng (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 701 - 706
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