Title | A Formal Approach to Debug Polynomial Datapath Designs |
Author | *Bijan Alizadeh (Univ. of Tehran, Iran) |
Page | pp. 683 - 688 |
Detailed information (abstract, keywords, etc) |
Title | Automated Debugging of Counterexamples in Formal Verification of Pipelined Microprocessors |
Author | *Miroslav N. Velev, Ping Gao (Aries Design Automation, U.S.A.) |
Page | pp. 689 - 694 |
Detailed information (abstract, keywords, etc) |
Title | On Error Tolerance and Engineering Change with Partially Programmable Circuits |
Author | Hratch Mangassarian (Univ. of Toronto, Canada), Hiroaki Yoshida (Univ. of Tokyo, Japan), Andreas Veneris (Univ. of Toronto, Canada), Shigeru Yamashita (Ritsumeikan Univ., Japan), *Masahiro Fujita (Univ. of Tokyo, Japan) |
Page | pp. 695 - 700 |
Detailed information (abstract, keywords, etc) |
Title | On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation |
Author | Ming Gao, *Peter Lisherness (Univ. of California, Santa Barbara, U.S.A.), Jing-Jia Liou (National Tsing Hua Univ., Taiwan), Kwang-Ting (Tim) Cheng (Univ. of California, Santa Barbara, U.S.A.) |
Page | pp. 701 - 706 |
Detailed information (abstract, keywords, etc) |