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The 17th Asia and South Pacific Design Automation Conference

Session S5  Special Session 5: Advanced Post-silicon Validation and Debugging Techniques for SoC
Time: 14:00 - 15:40 Wednesday, February 1, 2012
Location: Room 204A
Chair: Masahiro Fujita (Univ. of Tokyo, Japan)

S5-1 (Time: 14:00 - 14:25)
Title(Invited Paper) Bug Localization Techniques for Effective Post-Silicon Validation
Author*Subhasish Mitra, David Lin (Stanford Univ., U.S.A.), Nagib Hakim, Don Gardner (Intel Corp., U.S.A.)
Pagep. 291
Detailed information (abstract, keywords, etc)

S5-2 (Time: 14:25 - 14:50)
Title(Invited Paper) Improving Validation Coverage Metrics to Account for Limited Observability
Author*Peter Lisherness, Kwang-Ting (Tim) Cheng (UCSB, U.S.A.)
Pagepp. 292 - 297
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S5-3 (Time: 14:50 - 15:15)
Title(Invited Paper) Automated Data Analysis Techniques for a Modern Silicon Debug Environment
Author*Yu-Shen Yang (Vennsa Technologies, Canada), Andreas Veneris (Univ. of Toronto, Canada), Nicola Nicolici (McMaster Univ., Canada), Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 298 - 303
Detailed information (abstract, keywords, etc)

S5-4 (Time: 15:15 - 15:40)
Title(Invited Paper) Optimizing Test-Generation to the Execution Platform
AuthorAmir Nahir, *Avi Ziv (IBM Research, Israel), Subrat Panda (IBM, India)
Pagepp. 304 - 309
Detailed information (abstract, keywords, etc)