The 17th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, January 30, 2012

Tutorial 1: Design for Manufacturability and Reliability in Nanoscale CMOS and 3D-IC
9:00 - 17:00

Tutorial 2: Wireless Body Sensor Network (WBSN) Design
9:00 - 17:00

Tutorial 3: Heterogeneity for Power Management: Devices to Systems
9:00 - 17:00

Tutorial 4: Energy Efficiency in Scalable Power Sources: Portable to Grid-Connected Systems
9:00 - 17:00

Tutorial 5: Assertion-based verification for SoC and embedded software
9:00 - 17:00

Tuesday, January 31, 2012

Room 204A	Room 204B	Room 203	Room 202
1K (Room 204A+204B) Opening & Keynote 1 8:30 - 9:50
Coffee Break 9:50 - 10:20
2K (Room 204A+204B) Keynote 2 10:20 - 11:10
3K (Room 204A+204B) Keynote 3 11:10 - 12:00
Lunch 12:00 - 14:00
S1 Special Session 1: Robust and Resilient Designs from the Bottom-Up: Technology, CAD, Circuit, and System Issues 14:00 - 15:40	1A Architecture Issues in Embedded Systems 14:00 - 15:40	1B Power Network Design and Analysis 14:00 - 15:40	1C Emerging Circuits and Memories 14:00 - 15:40
Coffee Break 15:40 - 16:10
S2 Special Session 2: Domain Specific Accelerators 16:10 - 17:50	2A System-Level Optimization Techniques for Multi-Core Architectures 16:10 - 17:50	2B High-Speed PCB Routing 16:10 - 17:50	2C Emerging Test Solutions 16:10 - 17:50

Wednesday, February 1, 2012

Room 204A	Room 204B	Room 203	Room 202
I1 (Room 204A) Invited Talk 1 8:30 - 9:20
I2 (Room 204A) Invited Talk 2 9:20 - 10:10
Coffee Break 10:10 - 10:40
S3 Special Session 3: Design and Prototyping of Invasive MPSoC Architectures 10:40 - 12:20	S4 Special Session 4: Making ESL Models Work 10:40 - 12:20	3B High-Level Synthesis 10:40 - 12:20	3C Yield and Manufacturability Enhancement 10:40 - 12:20
Lunch 12:20 - 14:00
S5 Special Session 5: Advanced Post-silicon Validation and Debugging Techniques for SoC 14:00 - 15:40	S6 Special Session 6: Design and Architecture of Emerging Non-volatile Memory Technologies 14:00 - 15:40	4B 3D IC Layout 14:00 - 15:40	4C Simulation and Modeling for Signal-Integrity Analysis 14:00 - 15:40
Coffee Break 15:40 - 16:10
S7 Special Session 7: Sensor Node Optimization in Machine-to-Machine (M2M) Networks 16:10 - 17:50	5A Adaptive and Power-Efficient NoC Architectures 16:10 - 17:25	5B Physical Optimization for Power and Timing 16:10 - 17:50	5C Parallelizing System-Level Simulation 16:10 - 17:25

Thursday, February 2, 2012

Room 204A	Room 204B	Room 203	Room 202
D1 University LSI Design Contest 1 8:30 - 10:10	6A Efficient Methods for Resource Utilization in Multi-Core NoC Designs 8:30 - 10:10	6B Circuit-Level Timing Optimization 8:30 - 10:10	6C Modeling and Simulation for Nanoscale Analog Circuits 8:30 - 10:10
Coffee Break 10:10 - 10:40
D2 University LSI Design Contest 2 10:40 - 12:20	7A System-Level Modeling, Simulation, and Verification 10:40 - 12:20	7B Timing, Thermal, and Power Issues in High-Performance Design 10:40 - 12:20	7C Interconnect, Cooling, and Charge Storage Technologies 10:40 - 12:20
Lunch 12:20 - 14:00
S8 Special Session 8: Design for Reconfigurability and Adaptivity: Device, Circuit and System Perspectives 14:00 - 15:40	8A Scheduling for Embedded and High-Performance Systems 14:00 - 15:40	8B Automated Debugging and Validation 14:00 - 15:40	8C DFM for Nanolithography 14:00 - 15:40
Coffee Break 15:40 - 16:10
S9 Special Session 9: Quality Assurance for 3D-Stacked ICs 16:10 - 17:50	9A Design for System Reliability 16:10 - 17:50	9B Logic and Datapath Synthesis 16:10 - 17:50	9C Video, Display, and Signal Processing Technologies and Techniques 16:10 - 17:50

List of Papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 31, 2012

Session 1K Opening & Keynote 1
Time: 8:30 - 9:50 Tuesday, January 31, 2012
Location: Room 204A+204B

1K-1 (Time: 8:30 - 9:20)

Title	(Keynote Address) Engineering Complex Systems for Health, Security and the Environment
Author	*Giovanni De Micheli (EPF Lausanne, Switzerland)
Page	pp. 1 - 6
Detailed information (abstract, keywords, etc)

Session 2K Keynote 2
Time: 10:20 - 11:10 Tuesday, January 31, 2012
Location: Room 204A+204B

2K-1 (Time: 10:20 - 11:10)

Title	(Keynote Address) Antipodean VLSI Adventures
Author	Neil Weste (OzRunways Pty. Ltd, Australia)
Detailed information (abstract, keywords, etc)

Session 3K Keynote 3
Time: 11:10 - 12:00 Tuesday, January 31, 2012
Location: Room 204A+204B

3K-1 (Time: 11:10 - 12:00)

Title	(Keynote Address) Trends, Challenges and Solutions of Design Ecosystem for 20nm and Beyond
Author	Cliff Hou (Taiwan Semiconductor Manufacturing Co. Ltd., Taiwan)
Detailed information (abstract, keywords, etc)

Session S1 Special Session 1: Robust and Resilient Designs from the Bottom-Up: Technology, CAD, Circuit, and System Issues
Time: 14:00 - 15:40 Tuesday, January 31, 2012
Location: Room 204A
Chair: Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)

S1-1

Title	(Invited Paper) Robust and Resilient Designs from the Bottom-Up: Technology, CAD, Circuit, and System Issues
Author	Vijay J. Reddi, David Z. Pan (Univ. of Texas, Austin, U.S.A.), Sani Nassif (IBM, U.S.A.), Keith A. Bowman (Intel, U.S.A.)
Page	pp. 7 - 16
Detailed information (abstract, keywords, etc)

S1-2 (Time: 14:00 - 14:25)

Title	(Invited Paper) Technology Challenges beyond 22nm
Author	*Sani Nassif (IBM, U.S.A.)
Detailed information (abstract, keywords, etc)

S1-3 (Time: 14:25 - 14:50)

Title	(Invited Paper) Physical CAD for Robust Designs
Author	*David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Detailed information (abstract, keywords, etc)

S1-4 (Time: 14:50 - 15:15)

Title	(Invited Paper) Resilient Circuit Design Trade-Offs for Improving Performance & Energy Efficiency
Author	*Keith A. Bowman (Intel, U.S.A.)
Detailed information (abstract, keywords, etc)

S1-5 (Time: 15:15 - 15:40)

Title	(Invited Paper) Coordinated System Design for Resiliency
Author	*Vijay J. Reddi (Univ. of Texas, Austin, U.S.A.)
Detailed information (abstract, keywords, etc)

Session 1A Architecture Issues in Embedded Systems
Time: 14:00 - 15:40 Tuesday, January 31, 2012
Location: Room 204B
Chairs: Tei-Wei Kuo (National Taiwan Univ., Taiwan), Zili Shao (Hong Kong Polytechnic Univ.)

1A-1 (Time: 14:00 - 14:25)

Title	JOP-Plus - A Processor for Efficient Execution of Java Programs Extended with GALS Concurrency
Author	Muhammad Nadeem, *Morteza Biglari-Abhari, Zoran Salcic (Univ. of Auckland, New Zealand)
Page	pp. 17 - 22
Detailed information (abstract, keywords, etc)

1A-2 (Time: 14:25 - 14:50)

Title	An Application Classification Guided Cache Tuning Heuristic for Multi-core Architectures
Author	Marisha Rawlins, *Ann Gordon-Ross (Univ. of Florida, U.S.A.)
Page	pp. 23 - 28
Detailed information (abstract, keywords, etc)

1A-3 (Time: 14:50 - 15:15)

Title	Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation
Author	*Leandro Fiorin, Alberto Ferrante, Konstantinos Padarnitas, Francesco Regazzoni (Univ. of Lugano, Switzerland)
Page	pp. 29 - 34
Detailed information (abstract, keywords, etc)

1A-4 (Time: 15:15 - 15:40)

Title	PRR: A Low-Overhead Cache Replacement Algorithm for Embedded Processors
Author	Wei-Che Tseng (Univ. of Texas, Dallas, U.S.A.), *Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Qingfeng Zhuge, Jingtong Hu, Edwin H.-M. Sha (Univ. of Texas, Dallas, U.S.A.)
Page	pp. 35 - 40
Detailed information (abstract, keywords, etc)

Session 1B Power Network Design and Analysis
Time: 14:00 - 15:40 Tuesday, January 31, 2012
Location: Room 203
Chairs: Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Saibal Mukhopadhyay (Georgia Tech, U.S.A.)

1B-1 (Time: 14:00 - 14:25)

Title	Incremental Power Network Analysis Using Backward Random Walks
Author	*Baktash Boghrati, Sachin Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 41 - 46
Detailed information (abstract, keywords, etc)

1B-2 (Time: 14:25 - 14:50)

Title	Thermal-aware Power Network Design for IR Drop Reduction in 3D ICs
Author	*Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang (Tsinghua Univ., China), Tingting Huang (National Tsing Hua Univ., China), Yuan Xie (Pennsylvania State Univ., U.S.A.)
Page	pp. 47 - 52
Detailed information (abstract, keywords, etc)

1B-3 (Time: 14:50 - 15:15)

Title	The Feasibility of Carbon Nanotubes for Power Delivery in 3-D Integrated Circuits
Author	*Nauman Khan, Soha Hassoun (Tufts Univ., U.S.A.)
Page	pp. 53 - 58
Detailed information (abstract, keywords, etc)

1B-4 (Time: 15:15 - 15:40)

Title	An Efficient Hamiltonian-Cycle Power-Switch Routing for MTCMOS Designs
Author	*Yi-Ming Wang (National Chiao Tung Univ., Taiwan), Shi-Hao Chen (Global Unichip Corp., Taiwan), Mango C.-T. Chao (National Chiao Tung Univ., Taiwan)
Page	pp. 59 - 65
Detailed information (abstract, keywords, etc)

Session 1C Emerging Circuits and Memories
Time: 14:00 - 15:40 Tuesday, January 31, 2012
Location: Room 202
Chairs: Yiran Chen (Univ. of Pittsburgh, U.S.A.), Hai Zhou (Northwestern Univ., U.S.A.)

1C-1 (Time: 14:00 - 14:25)

Title	An ILP-based Obstacle-Avoiding Routing Algorithm for Pin-Constrained EWOD Chips
Author	*Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Page	pp. 67 - 72
Detailed information (abstract, keywords, etc)

1C-2 (Time: 14:25 - 14:50)

Title	A Look Up Table Design with 3D Bipolar RRAMs
Author	Yi-Chung Chen (Polytechnic Inst. of New York Univ., U.S.A.), *Wei Zhang (Nanyang Technological Univ., Singapore), Hai Li (Polytechnic Inst. of New York Univ., U.S.A.)
Page	pp. 73 - 78
Detailed information (abstract, keywords, etc)

1C-3 (Time: 14:50 - 15:15)

Title	Low Power Memristor-Based ReRAM Design with Error Correcting Code
Author	*Dimin Niu, Yang Xiao, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Page	pp. 79 - 84
Detailed information (abstract, keywords, etc)

1C-4 (Time: 15:15 - 15:40)

Title	Synthesis of Reversible Circuits with Minimal Lines for Large Functions
Author	Mathias Soeken, *Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 85 - 92
Detailed information (abstract, keywords, etc)

Session S2 Special Session 2: Domain Specific Accelerators
Time: 16:10 - 17:50 Tuesday, January 31, 2012
Location: Room 204A
Chair: Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.)

S2-1 (Time: 16:10 - 16:30)

Title	(Invited Paper) Accelerated Processing and the Fusion System Architecture
Author	*Mike O'Connor (AMD Research, Texas, U.S.A.)
Page	p. 93
Detailed information (abstract, keywords, etc)

S2-2 (Time: 16:30 - 16:50)

Title	(Invited Paper) Platform Characterization for Domain-Specific Computing
Author	*Alex Bui (Univ. of California, Los Angeles, U.S.A.), Kwang-Ting (Tim) Cheng (Univ. of California, Santa Barbara, U.S.A.), Jason Cong, Luminita Vese (Univ. of California, Los Angeles, U.S.A.), Yi-Chu Wang (Univ. of California, Santa Barbara, U.S.A.), Bo Yuan, Yi Zou (Univ. of California, Los Angeles, U.S.A.)
Page	pp. 94 - 99
Detailed information (abstract, keywords, etc)

S2-3 (Time: 16:50 - 17:10)

Title	(Invited Paper) GreenDroid: An Architecture for the Dark Silicon Age
Author	Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng, Vikram Bhatt, Joe Auricchio, Steven Swanson, *Michael Bedford Taylor (Univ. of California, San Diego, U.S.A.)
Page	pp. 100 - 105
Detailed information (abstract, keywords, etc)

S2-4 (Time: 17:10 - 17:30)

Title	(Invited Paper) Accelerator-Rich Architectures: Implications, Opportunities and Challenges
Author	*Ravi Iyer (Intel, U.S.A.)
Page	pp. 106 - 107
Detailed information (abstract, keywords, etc)

S2-5 (Time: 17:30 - 17:50)

Title	(Invited Paper) A Reconfigurable Platform for the Design and Verification of Domain-Specific Accelerators
Author	Sungho Park, Yong Cheol, Peter Cho, Kevin M. Irick, *Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.)
Page	pp. 108 - 113
Detailed information (abstract, keywords, etc)

Session 2A System-Level Optimization Techniques for Multi-Core Architectures
Time: 16:10 - 17:50 Tuesday, January 31, 2012
Location: Room 204B
Chairs: Kiyoung Choi (Seoul National Univ., Republic of Korea), Yuko Hara-Azumi (Ritsumeikan Univ., Japan)

2A-1 (Time: 16:10 - 16:35)

Title	Learning-Based Power Management for Multi-Core Processors via Idle Period Manipulation
Author	Rong Ye, *Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 115 - 120
Detailed information (abstract, keywords, etc)

2A-2 (Time: 16:35 - 17:00)

Title	Memory Access Aware Power Gating for MPSoCs
Author	*Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang (National Taiwan Univ., Taiwan), Naehyuck Chang (Seoul National Univ., Republic of Korea)
Page	pp. 121 - 126
Detailed information (abstract, keywords, etc)

2A-3 (Time: 17:00 - 17:25)

Title	Buffer Minimization in Pipelined SDF Scheduling on Multi-Core Platforms
Author	Yuankai Chen, *Hai Zhou (Northwestern Univ., U.S.A.)
Page	pp. 127 - 132
Detailed information (abstract, keywords, etc)

2A-4 (Time: 17:25 - 17:50)

Title	A Hierarchical C2RTL Framework for FIFO-Connected Stream Applications
Author	*Shuangchen Li, Yongpan Liu, Daming Zhang, Xinyu He (Tsinghua Univ., China), Pei Zhang (Y Explorations Inc., U.S.A.), Huazhong Yang (Tsinghua Univ., China)
Page	pp. 133 - 138
Detailed information (abstract, keywords, etc)

Session 2B High-Speed PCB Routing
Time: 16:10 - 17:50 Tuesday, January 31, 2012
Location: Room 203
Chairs: Yih-Lang Li (National Chiao Tung Univ., Taiwan), Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)

2B-1 (Time: 16:10 - 16:35)

Title	Escape Routing of Differential Pairs Considering Length Matching
Author	*Tai-Hung Li, Wan-Chun Chen, Xian-Ting Cai, Tai-Chen Chen (National Central Univ., Taiwan)
Page	pp. 139 - 144
Detailed information (abstract, keywords, etc)

2B-2 (Time: 16:35 - 17:00)

Title	An Any-Angle Routing Method using Quasi-Newton Method
Author	*Yukihide Kohira (Univ. of Aizu, Japan), Atsushi Takahashi (Osaka Univ., Japan)
Page	pp. 145 - 150
Detailed information (abstract, keywords, etc)

2B-3 (Time: 17:00 - 17:25)

Title	Linear Optimal One-Sided Single-Detour Algorithm for Untangling Twisted Bus
Author	Tao Lin, *Sheqin Dong (Tsinghua Univ., China), Song Chen, Satoshi Goto (Waseda Univ., Japan)
Page	pp. 151 - 156
Detailed information (abstract, keywords, etc)

2B-4 (Time: 17:25 - 17:50)

Title	LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits
Author	*Hailong Yao, Yici Cai, Qiang Gao (Tsinghua Univ., China)
Page	pp. 157 - 162
Detailed information (abstract, keywords, etc)

Session 2C Emerging Test Solutions
Time: 16:10 - 17:50 Tuesday, January 31, 2012
Location: Room 202
Chairs: Jiun-Lang Huang (National Taiwan Univ., Taiwan), Wu-Tung Cheng (Mentor Graphics, U.S.A.)

2C-1 (Time: 16:10 - 16:35)

Title	An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
Author	Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, *Charles H.-P. Wen (National Chiao Tung Univ., Taiwan), Jayanta Bhadra (Freescale Semiconductor Inc., U.S.A.)
Page	pp. 163 - 168
Detailed information (abstract, keywords, etc)

2C-2 (Time: 16:35 - 17:00)

Title	CODA: A Concurrent Online Delay Measurement Architecture for Critical Paths
Author	Yubin Zhang (Chinese Academy of Sciences, China), Haile Yu, *Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 169 - 174
Detailed information (abstract, keywords, etc)

2C-3 (Time: 17:00 - 17:25)

Title	Low-cost Control Flow Error Protection by Exploiting Available Redundancies in the Pipeline
Author	Mohammad Abdur Rouf, *Soontae Kim (KAIST, Republic of Korea)
Page	pp. 175 - 180
Detailed information (abstract, keywords, etc)

2C-4 (Time: 17:25 - 17:50)

Title	Detection and Diagnosis of Faulty Quantum Circuits
Author	*Alexandru Paler, Ilia Polian (Univ. of Passau, Germany), John P. Hayes (Univ. of Michigan, U.S.A.)
Page	pp. 181 - 186
Detailed information (abstract, keywords, etc)

Wednesday, February 1, 2012

Session I1 Invited Talk 1
Time: 8:30 - 9:20 Wednesday, February 1, 2012
Location: Room 204A

I1-1 (Time: 8:30 - 9:20)

Title	(Invited Paper) Achieving Energy Efficiency by Dynamic Techniques
Author	Tanay Karnik, Karnik Tschanz, Keith Bowman, Carlos Tokunaga, Vivek De, Shekhar Borkar (Intel, U.S.A.)
Detailed information (abstract, keywords, etc)

Session I2 Invited Talk 2
Time: 9:20 - 10:10 Wednesday, February 1, 2012
Location: Room 204A

I2-1 (Time: 9:20 - 10:10)

Title	(Invited Paper) Multi-Threaded Processing Paradigms for Scalable Media Compression
Author	David Taubman (Univ. of New South Wales, Australia)
Detailed information (abstract, keywords, etc)

Session S3 Special Session 3: Design and Prototyping of Invasive MPSoC Architectures
Time: 10:40 - 12:20 Wednesday, February 1, 2012
Location: Room 204A
Chair: Sri Parameswaran (Univ. of New South Wales, Australia)

S3-1 (Time: 10:40 - 11:05)

Title	(Invited Paper) Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs
Author	Sascha Roloff, Frank Hannig, Jürgen Teich (Univ. of Erlangen-Nuremberg, Germany)
Page	pp. 187 - 192
Detailed information (abstract, keywords, etc)

S3-2 (Time: 11:05 - 11:30)

Title	(Invited Paper) Invasive Manycore Architectures
Author	Jörg Henkel (Karlsruhe Inst. of Tech., Germany), Andreas Herkersdorf (Tech. Univ. of Munich, Germany), Lars Bauer (Karlsruhe Inst. of Tech., Germany), Thomas Wild (Tech. Univ. of Munich, Germany), Michael Hubner (Karlsruhe Inst. of Tech., Germany), Ravi Kumar Pujari (Tech. Univ. of Munich, Germany), Artjom Grudnitsky, Jan Heisswolf (Karlsruhe Inst. of Tech., Germany), Aurang Zaib (Tech. Univ. of Munich, Germany), Benjamin Vogel (Karlsruhe Inst. of Tech., Germany), Vahid Lari (Univ. of Erlangen-Nuremberg, Germany), Sebastian Kobbe (Karlsruhe Inst. of Tech., Germany)
Page	pp. 193 - 200
Detailed information (abstract, keywords, etc)

S3-3 (Time: 11:30 - 11:55)

Title	(Invited Paper) Hardware Prototyping of Novel Invasive Multicore Architectures
Author	Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig (Karlsruhe Inst. of Tech., Germany), David May (Technische Univ. München, Germany)
Page	pp. 201 - 206
Detailed information (abstract, keywords, etc)

S3-4 (Time: 11:55 - 12:20)

Title	(Invited Paper) Invasive Computing for Robotic Vision
Author	Johny Paul, Walter Stechele (Tech. Univ. of Munich, Germany), M. Kröhnert, T. Asfour, R. Dillmann (Karlsruhe Inst. of Tech., Germany)
Page	pp. 207 - 212
Detailed information (abstract, keywords, etc)

Session S4 Special Session 4: Making ESL Models Work
Time: 10:40 - 12:20 Wednesday, February 1, 2012
Location: Room 204B
Chair: Gunar Schirner (Northeastern Univ., U.S.A.)

S4-1 (Time: 10:40 - 11:05)

Title	(Invited Paper) Abstract System-Level Models for Early Performance and Power Exploration
Author	*Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi (Univ. of Texas, Austin, U.S.A.)
Page	pp. 213 - 218
Detailed information (abstract, keywords, etc)

S4-2 (Time: 11:05 - 11:30)

Title	(Invited Paper) Virtual Prototyping of Cyber-Physical Systems
Author	*Wolfgang Mueller, Markus Becker, Ahmed Elfeky (Univ. of Paderborn/C-LAB, Germany), Anthony DiPasquale (Northwestern Univ., U.S.A.)
Page	pp. 219 - 226
Detailed information (abstract, keywords, etc)

S4-3 (Time: 11:30 - 11:55)

Title	(Invited Paper) Parallel Discrete Event Simulation of Transaction Level Models
Author	*Rainer Doemer, Weiwei Chen, Xu Han (Univ. of California, Irvine, U.S.A.)
Page	pp. 227 - 231
Detailed information (abstract, keywords, etc)

S4-4 (Time: 11:55 - 12:20)

Title	(Invited Paper) Post-Silicon Patching for Verification/Debugging with High-Level Models and Programmable Logic
Author	*Masahiro Fujita, Hiroaki Yoshida (Univ. of Tokyo/CREST, JST, Japan)
Page	pp. 232 - 237
Detailed information (abstract, keywords, etc)

Session 3B High-Level Synthesis
Time: 10:40 - 12:20 Wednesday, February 1, 2012
Location: Room 203
Chairs: Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan)

3B-1 (Time: 10:40 - 11:05)

Title	Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range
Author	*Keisuke Inoue, Mineo Kaneko (JAIST, Japan)
Page	pp. 239 - 244
Detailed information (abstract, keywords, etc)

3B-2 (Time: 11:05 - 11:30)

Title	Clock Period Minimization with Minimum Area Overhead in High-Level Synthesis of Nonzero Clock Skew Circuits
Author	*Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan)
Page	pp. 245 - 250
Detailed information (abstract, keywords, etc)

3B-3 (Time: 11:30 - 11:55)

Title	Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis
Author	*Yuko Hara-Azumi, Hiroyuki Tomiyama (Ritsumeikan Univ., Japan)
Page	pp. 251 - 256
Detailed information (abstract, keywords, etc)

3B-4 (Time: 11:55 - 12:20)

Title	An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis
Author	*Yuxin Wang (Peking Univ. and UCLA/PKU Joint Research Inst. in Science and Engineering, China), Peng Zhang (Univ. of California, Los Angeles, U.S.A.), Xu Cheng (Peking Univ., China), Jason Cong (Univ. of California, Los Angeles and UCLA/PKU Joint Research Inst. in Science and Engineering, U.S.A.)
Page	pp. 257 - 262
Detailed information (abstract, keywords, etc)

Session 3C Yield and Manufacturability Enhancement
Time: 10:40 - 12:20 Wednesday, February 1, 2012
Location: Room 202
Chairs: Zheng Shi (Zhejiang Univ., China), Charles H.-P. Wen (National Chiao Tung Univ., Taiwan)

3C-1 (Time: 10:40 - 11:05)

Title	EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation
Author	Duo Ding, Bei Yu, Joydeep Ghosh, *David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 263 - 270
Detailed information (abstract, keywords, etc)

3C-2 (Time: 11:05 - 11:30)

Title	GNOMO: Greater-than-NOMinal V_dd Operation for BTI Mitigation
Author	*Saket Gupta, Sachin Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 271 - 276
Detailed information (abstract, keywords, etc)

3C-3 (Time: 11:30 - 11:55)

Title	Tier-Adaptive-Voltage-Scaling (TAVS): A Methodology for Post-Silicon Tuning of 3D ICs
Author	Kwanyeob Chae, *Saibal Mukhopadhyay (Georgia Tech, U.S.A.)
Page	pp. 277 - 282
Detailed information (abstract, keywords, etc)

3C-4 (Time: 11:55 - 12:20)

Title	Body Bias Clustering for Low Test-Cost Post-Silicon Tuning
Author	Shuta Kimura, *Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)
Page	pp. 283 - 289
Detailed information (abstract, keywords, etc)

Session S5 Special Session 5: Advanced Post-silicon Validation and Debugging Techniques for SoC
Time: 14:00 - 15:40 Wednesday, February 1, 2012
Location: Room 204A
Chair: Masahiro Fujita (Univ. of Tokyo, Japan)

S5-1 (Time: 14:00 - 14:25)

Title	(Invited Paper) Bug Localization Techniques for Effective Post-Silicon Validation
Author	*Subhasish Mitra, David Lin (Stanford Univ., U.S.A.), Nagib Hakim, Don Gardner (Intel Corp., U.S.A.)
Page	p. 291
Detailed information (abstract, keywords, etc)

S5-2 (Time: 14:25 - 14:50)

Title	(Invited Paper) Improving Validation Coverage Metrics to Account for Limited Observability
Author	*Peter Lisherness, Kwang-Ting (Tim) Cheng (UCSB, U.S.A.)
Page	pp. 292 - 297
Detailed information (abstract, keywords, etc)

S5-3 (Time: 14:50 - 15:15)

Title	(Invited Paper) Automated Data Analysis Techniques for a Modern Silicon Debug Environment
Author	*Yu-Shen Yang (Vennsa Technologies, Canada), Andreas Veneris (Univ. of Toronto, Canada), Nicola Nicolici (McMaster Univ., Canada), Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 298 - 303
Detailed information (abstract, keywords, etc)

S5-4 (Time: 15:15 - 15:40)

Title	(Invited Paper) Optimizing Test-Generation to the Execution Platform
Author	Amir Nahir, *Avi Ziv (IBM Research, Israel), Subrat Panda (IBM, India)
Page	pp. 304 - 309
Detailed information (abstract, keywords, etc)

Session S6 Special Session 6: Design and Architecture of Emerging Non-volatile Memory Technologies
Time: 14:00 - 15:40 Wednesday, February 1, 2012
Location: Room 204B
Chair: Zili Shao (Hong Kong Polytechnic Univ., Hong Kong)

S6-1 (Time: 14:00 - 14:25)

Title	(Invited Paper) When to Forget: A System-level Perspective on STT-RAMs
Author	*Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.)
Page	pp. 311 - 316
Detailed information (abstract, keywords, etc)

S6-2 (Time: 14:25 - 14:50)

Title	(Invited Paper) Write-Activity-Aware Page Table Management for PCM-based Embedded Systems
Author	Tianzheng Wang, Duo Liu, *Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Chengmo Yang (Univ. of Delaware, U.S.A.)
Page	pp. 317 - 322
Detailed information (abstract, keywords, etc)

S6-3 (Time: 14:50 - 15:15)

Title	(Invited Paper) Probabilistic Design in Spintronic Memory and Logic Circuit
Author	*Yiran Chen, Yaojun Zhang, Peiyuan Wang (Univ. of Pittsburgh, U.S.A.)
Page	pp. 323 - 328
Detailed information (abstract, keywords, etc)

S6-4 (Time: 15:15 - 15:40)

Title	(Invited Paper) Endurance-Aware Circuit Designs of Nonvolatile Logic and Nonvolatile SRAM Using Resistive Memory (Memristor) Device
Author	*Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen (National Tsing Hua Univ., Taiwan), Hiroyuki Yamauchi (Fukuoka Inst. of Tech., Japan), Pi-Feng Chiu, Shyh-Shyuan Sheu (Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute (ITRI), Japan)
Page	pp. 329 - 334
Detailed information (abstract, keywords, etc)

Session 4B 3D IC Layout
Time: 14:00 - 15:40 Wednesday, February 1, 2012
Location: Room 203
Chairs: Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Yih-Lang Li (National Chiao Tung Univ., Taiwan)

4B-1 (Time: 14:00 - 14:25)

Title	Block-level 3D IC Design with Through-Silicon-Via Planning
Author	Dae Hyun Kim (Georgia Tech, U.S.A.), Rasit Onur Topaloglu (GLOBALFOUNDRIES, U.S.A.), *Sung Kyu Lim (Georgia Tech, U.S.A.)
Page	pp. 335 - 340
Detailed information (abstract, keywords, etc)

4B-2 (Time: 14:25 - 14:50)

Title	Micro-Bump Assignment for 3D ICs using Order Relation
Author	Ta-Yu Kuan, Yi-Chun Chang, *Tai-Chen Chen (National Central Univ., Taiwan)
Page	pp. 341 - 346
Detailed information (abstract, keywords, etc)

4B-3 (Time: 14:50 - 15:15)

Title	Through-Silicon-Via-Induced Obstacle-Aware Clock Tree Synthesis for 3D ICs
Author	Xin Zhao, *Sung Kyu Lim (Georgia Tech, U.S.A.)
Page	pp. 347 - 352
Detailed information (abstract, keywords, etc)

4B-4 (Time: 15:15 - 15:40)

Title	Parallel Implementation of R-trees on the GPU
Author	Lijuan Luo (Univ. of Illinois, Urbana-Champaign/NVIDIA Corp., U.S.A.), *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Lance Leong (NVIDIA Corp., U.S.A.)
Page	pp. 353 - 358
Detailed information (abstract, keywords, etc)

Session 4C Simulation and Modeling for Signal-Integrity Analysis
Time: 14:00 - 15:40 Wednesday, February 1, 2012
Location: Room 202
Chairs: Rung-Bin Lin (Yuan Ze Univ., Taiwan), Youngsoo Shin (KAIST, Republic of Korea)

4C-1 (Time: 14:00 - 14:25)

Title	An Adaptive LU Factorization Algorithm for Parallel Circuit Simulation
Author	*Xiaoming Chen, Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 359 - 364
Detailed information (abstract, keywords, etc)

4C-2 (Time: 14:25 - 14:50)

Title	Predictor-Corrector Latency Insertion Method for Fast Transient Analysis of Ill-Constructed Circuits
Author	*Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ., Japan)
Page	pp. 365 - 370
Detailed information (abstract, keywords, etc)

4C-3 (Time: 14:50 - 15:15)

Title	Crosstalk-Aware Statistical Interconnect Delay Calculation
Author	*Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs (Delft Univ. of Tech., Netherlands)
Page	pp. 371 - 376
Detailed information (abstract, keywords, etc)

4C-4 (Time: 15:15 - 15:40)

Title	Fast Floating Random Walk Algorithm for Multi-Dielectric Capacitance Extraction with Numerical Characterization of Green's Functions
Author	Hao Zhuang (Tsinghua Univ./Peking Univ., China), *Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye (Tsinghua Univ., China)
Page	pp. 377 - 382
Detailed information (abstract, keywords, etc)

Session S7 Special Session 7: Sensor Node Optimization in Machine-to-Machine (M2M) Networks
Time: 16:10 - 17:50 Wednesday, February 1, 2012
Location: Room 204A
Chairs: Tei-Wei Kuo (National Taiwan Univ., Taiwan), Yen-Kuang Chen (Intel Corp., U.S.A.)

S7-1 (Time: 16:10 - 16:35)

Title	(Invited Paper) Challenges and Opportunities of Internet of Things
Author	*Yen-Kuang Chen (Intel Corp., U.S.A.)
Page	pp. 383 - 388
Detailed information (abstract, keywords, etc)

S7-2 (Time: 16:35 - 17:00)

Title	(Invited Paper) Application Specific Sensor Node Architecture Optimization --- Experiences from Field Deployments
Author	*Wei Liu, Xiaotian Fei, Tao Tang, Pengjun Wang, Hong Luo, Beixing Deng, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 389 - 394
Detailed information (abstract, keywords, etc)

S7-3 (Time: 17:00 - 17:25)

Title	(Invited Paper) System-Wide Profiling and Optimization with Virtual Machines
Author	*Shih-Hao Hung, Tei-Wei Kuo, Chi-Sheng Shih (National Taiwan Univ., Taiwan), Chia-Heng Tu (Graduate Institute of Networking and Multimedia, Taiwan)
Page	pp. 395 - 400
Detailed information (abstract, keywords, etc)

S7-4 (Time: 17:25 - 17:50)

Title	(Invited Paper) Power Optimization of Wireless Video Sensor Nodes in M2M Networks
Author	*Shao-Yi Chien, Teng-Yuan Cheng, Chieh-Chuan Chiu, Pei-Kuei Tsung (National Taiwan Univ., Taiwan), Chia-han Lee (Academia Sinica, Taiwan), V. Srinivasa Somayazulu, Yen-Kuang Chen (Intel Corp., U.S.A.)
Page	pp. 401 - 405
Detailed information (abstract, keywords, etc)

Session 5A Adaptive and Power-Efficient NoC Architectures
Time: 16:10 - 17:25 Wednesday, February 1, 2012
Location: Room 204B
Chairs: Karam Chatha (Arizona State Univ.), Yu Wang (Tsinghua Univ., China)

5A-1 (Time: 16:10 - 16:35)

Title	A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs
Author	*Hiroki Matsutani, Yuto Hirata (Keio Univ., Japan), Michihiro Koibuchi (NII, Japan), Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Hiroshi Nakamura (Univ. of Tokyo, Japan), Hideharu Amano (Keio Univ., Japan)
Page	pp. 407 - 412
Detailed information (abstract, keywords, etc)

5A-2 (Time: 16:35 - 17:00)

Title	ARB-NET: A Novel Adaptive Monitoring Platform for Stacked Mesh 3D NoC Architectures
Author	*Amir-Mohammad Rahmani, Khalid Latif, Vaddina Kameswar Rao (Univ. of Turku/Turku Centre for Computer Science, Finland), Pasi Liljeberg, Juha Plosila, Hannu Tenhunen (Univ. of Turku, Finland)
Page	pp. 413 - 418
Detailed information (abstract, keywords, etc)

5A-3 (Time: 17:00 - 17:25)

Title	Memory-Aware Mapping and Scheduling of Tasks and Communications on Many-Core SoC
Author	*Jinho Lee, Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 419 - 424
Detailed information (abstract, keywords, etc)

Session 5B Physical Optimization for Power and Timing
Time: 16:10 - 17:50 Wednesday, February 1, 2012
Location: Room 203
Chairs: Sheqin Dong (Tsinghua Univ., China), Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)

5B-1 (Time: 16:10 - 16:35)

Title	A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function
Author	Suradeth Aroonsantidecha, *Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 425 - 430
Detailed information (abstract, keywords, etc)

5B-2 (Time: 16:35 - 17:00)

Title	Crosstalk-Aware Power Optimization with Multi-Bit Flip-Flops
Author	*Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan)
Page	pp. 431 - 436
Detailed information (abstract, keywords, etc)

5B-3 (Time: 17:00 - 17:25)

Title	Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization
Author	*Yen-Hung Lin, Yun-Jian Lo, Jian-Syun Tong, Wen-Hao Liu, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 437 - 442
Detailed information (abstract, keywords, etc)

5B-4 (Time: 17:25 - 17:50)

Title	Voltage Island-Driven Floorplanning Considering Level Shifter Placement
Author	Richard C.J. Hsu, Wei-Yi Cheng, Chung-Lin Lee, *Jai-Ming Lin (National Cheng Kung Univ., Taiwan)
Page	pp. 443 - 448
Detailed information (abstract, keywords, etc)

Session 5C Parallelizing System-Level Simulation
Time: 16:10 - 17:25 Wednesday, February 1, 2012
Location: Room 202
Chairs: Chia-Lin Yang (National Taiwan Univ., Taiwan), Derek Chiou (Univ. of Texas, Austin, U.S.A.)

5C-1 (Time: 16:10 - 16:35)

Title	Relaxed Synchronization Technique for Speeding-up the Parallel Simulation of Multiprocessor Systems
Author	Dukyoung Yun (Seoul National Univ., Republic of Korea), Sungchan Kim (Chonbuk National Univ., Republic of Korea), *Soonhoi Ha (Seoul National Univ., Republic of Korea)
Page	pp. 449 - 454
Detailed information (abstract, keywords, etc)

5C-2 (Time: 16:35 - 17:00)

Title	Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs
Author	*Rohit Sinha, Aayush Prakash, Hiren D. Patel (Univ. of Waterloo, Canada)
Page	pp. 455 - 460
Detailed information (abstract, keywords, etc)

5C-3 (Time: 17:00 - 17:25)

Title	An Optimizing Compiler for Out-of-Order Parallel ESL Simulation Exploiting Instance Isolation
Author	*Weiwei Chen, Rainer Doemer (Univ. of California, Irvine, U.S.A.)
Page	pp. 461 - 466
Detailed information (abstract, keywords, etc)

Thursday, February 2, 2012

Session D1 University LSI Design Contest 1
Time: 8:30 - 10:10 Thursday, February 2, 2012
Location: Room 204A

D1-1 (Time: 8:30 - 8:44)

Title	A 60-GHz 16QAM 11Gbps Direct-Conversion Transceiver in 65nm CMOS
Author	*Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chiavipas, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 467 - 468
Detailed information (abstract, keywords, etc)

D1-2 (Time: 8:44 - 8:58)

Title	A 120-mV Input, Fully Integrated Dual-Mode Charge Pump in 65-nm CMOS for Thermoelectric Energy Harvester
Author	*Po-Hung Chen, Koichi Ishida, Xin Zhang (Univ. of Tokyo, Japan), Yasuyuki Okuma, Yoshikatsu Ryu (STARC, Japan), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo, Japan)
Page	pp. 469 - 470
Detailed information (abstract, keywords, etc)

D1-3 (Time: 8:58 - 9:12)

Title	CMA-2 : The Second Prototype of a Low Power Reconfigurable Accelerator
Author	*Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ., Japan)
Page	pp. 471 - 472
Detailed information (abstract, keywords, etc)

D1-4 (Time: 9:12 - 9:26)

Title	Complexity-Effective Hilbert-Huang Transform (HHT) IP for Embedded Real-Time Applications
Author	Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, *Tay-Jyi Lin, Ching-Wei Yeh (National Chung Cheng Univ., Taiwan)
Page	pp. 473 - 474
Detailed information (abstract, keywords, etc)

D1-5 (Time: 9:26 - 9:40)

Title	Implementation of a Perpendicular MTJ-Based Read-Disturb-Tolerant 2T-2R Nonvolatile TCAM Based on a Reversed Current Reading Scheme
Author	*Shoun Matsunaga, Masanori Natsui, Shoji Ikeda (Tohoku Univ., Japan), Katsuya Miura (Hitachi Advanced Research Laboratory, Japan), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ., Japan)
Page	pp. 475 - 476
Detailed information (abstract, keywords, etc)

D1-6 (Time: 9:40 - 9:54)

Title	Energy-Efficient RISC Design with On-Demand Circuit-Level Timing Speculation
Author	*Tay-Jyi Lin (National Chung Cheng Univ., Taiwan), Yu-Ting Kuo (ITRI, Taiwan), Yu-Jung Tsai, Ting-Yu Shyu (National Chung Cheng Univ., Taiwan), Yuan-Hua Chu (ITRI, Taiwan)
Page	pp. 477 - 478
Detailed information (abstract, keywords, etc)

D1-7 (Time: 9:54 - 10:08)

Title	A 60mW Baseband SoC for CMMB Receiver
Author	*Chuan Wu, Jialin Cao, Dan Bao, Yun Chen, Xiaoyang Zeng (Fudan Univ., China)
Page	pp. 479 - 480
Detailed information (abstract, keywords, etc)

Session 6A Efficient Methods for Resource Utilization in Multi-Core NoC Designs
Time: 8:30 - 10:10 Thursday, February 2, 2012
Location: Room 204B
Chairs: Jiang Xu (Hong Kong Univ. of Science and Tech., Hong Kong), David Atienza (EPFL, Switzerland)

6A-1 (Time: 8:30 - 8:55)

Title	Proximity-Aware Cache Replication
Author	Chongmin Li, Dongsheng Wang, *Haixia Wang, Yibo Xue (Tsinghua Univ., China), Jian Li (IBM Research, U.S.A.)
Page	pp. 481 - 486
Detailed information (abstract, keywords, etc)

6A-2 (Time: 8:55 - 9:20)

Title	Dynamic Reusability-based Replication with Network Address Mapping in CMPs
Author	Jinglei Wang, Dongsheng Wang, *Haixia Wang, Yibo Xue (Tsinghua Univ., China)
Page	pp. 487 - 492
Detailed information (abstract, keywords, etc)

6A-3 (Time: 9:20 - 9:45)

Title	Hungarian Algorithm Based Virtualization to Maintain Application Timing Similarity for Defect-Tolerant NoC
Author	Ke Yue, Frank Lockom, Zheng Li, Soumia Ghalim, *Shangping Ren (IIT, U.S.A.), Lei Zhang, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 493 - 498
Detailed information (abstract, keywords, etc)

6A-4 (Time: 9:45 - 10:10)

Title	Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs
Author	*Hany Kashif, Hiren D. Patel, Sebastian Fischmeister (Univ. of Waterloo, Canada)
Page	pp. 499 - 504
Detailed information (abstract, keywords, etc)

Session 6B Circuit-Level Timing Optimization
Time: 8:30 - 10:10 Thursday, February 2, 2012
Location: Room 203
Chairs: Sachin Sapatnekar (Univ. of Minnesota, U.S.A.), Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)

6B-1 (Time: 8:30 - 8:55)

Title	A Semi-Formal Min-Cost Buffer Insertion Technique Considering Multi-Mode Multi-Corner Timing Constraints
Author	*Shih Heng Tsai, Man Yu Li, Chung Yang Huang (National Taiwan Univ., Taiwan)
Page	pp. 505 - 510
Detailed information (abstract, keywords, etc)

6B-2 (Time: 8:55 - 9:20)

Title	ECO Timing Optimization with Negotiation-Based Re-Routing and Logic Re-Structuring Using Spare Cells
Author	Xing Wei, *Wai-Chung Tang, Yi Diao, Yu-Liang Wu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 511 - 516
Detailed information (abstract, keywords, etc)

6B-3 (Time: 9:20 - 9:45)

Title	Clock Rescheduling for Timing Engineering Change Orders
Author	*Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang (National Taiwan Univ., Taiwan)
Page	pp. 517 - 522
Detailed information (abstract, keywords, etc)

6B-4 (Time: 9:45 - 10:10)

Title	Optimal Prescribed-Domain Clock Skew Scheduling
Author	Li Li, Yinghai Lu, *Hai Zhou (Northwestern Univ., U.S.A.)
Page	pp. 523 - 527
Detailed information (abstract, keywords, etc)

Session 6C Modeling and Simulation for Nanoscale Analog Circuits
Time: 8:30 - 10:10 Thursday, February 2, 2012
Location: Room 202
Chairs: Ngai Wong (Univ. of Hong Kong, Hong Kong), Hao Yu (Nanyang Technological Univ., Singapore)

6C-1 (Time: 8:30 - 8:55)

Title	Fast Simulation of Hybrid CMOS and STT-MTJ Circuits with Identified Internal State Variables
Author	Yang Shang, Wei Fei, *Hao Yu (Nanyang Technological Univ., Singapore)
Page	pp. 529 - 534
Detailed information (abstract, keywords, etc)

6C-2 (Time: 8:55 - 9:20)

Title	Time-Domain Performance Bound Analysis of Analog Circuits Considering Process Variations
Author	Xue-Xin Liu, *Sheldon X.-D. Tan, Zhigang Hao (Univ. of California, Riverside, U.S.A.), Guoyong Shi (Shanghai Jiao Tong Univ., China)
Page	pp. 535 - 540
Detailed information (abstract, keywords, etc)

6C-3 (Time: 9:20 - 9:45)

Title	Hierarchical Graph Reduction Approach to Symbolic Circuit Analysis with Data Sharing and Cancellation-Free Properties
Author	Yang Song, *Guoyong Shi (Shanghai Jiao Tong Univ., China)
Page	pp. 541 - 546
Detailed information (abstract, keywords, etc)

6C-4 (Time: 9:45 - 10:10)

Title	Weakly Nonlinear Circuit Analysis Based on Fast Multidimensional Inverse Laplace Transform
Author	*Tingting Wang, Haotian Liu, Yuanzhe Wang, Ngai Wong (Univ. of Hong Kong, Hong Kong)
Page	pp. 547 - 552
Detailed information (abstract, keywords, etc)

Session D2 University LSI Design Contest 2
Time: 10:40 - 12:20 Thursday, February 2, 2012
Location: Room 204A

D2-1 (Time: 10:40 - 10:54)

Title	A Reference-Free On-Chip Timing Jitter Measurement Circuit Using Self-Referenced Clock and a Cascaded Time Difference Amplifier in 65nm CMOS
Author	*Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi (Gunma Univ., Japan)
Page	pp. 553 - 554
Detailed information (abstract, keywords, etc)

D2-2 (Time: 10:54 - 11:08)

Title	Simultaneous Data and Power Transmission using Nested Clover Coils
Author	*Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda (Keio Univ., Japan)
Page	pp. 555 - 556
Detailed information (abstract, keywords, etc)

D2-3 (Time: 11:08 - 11:22)

Title	Complexity-Effective Auditory Compensation with a Controllable Filter for Digital Hearing Aids
Author	Ya-Ting Chang, *Kuo-Chiang Chang, Yu-Ting Kuo, Chih-Wei Liu (National Chiao Tung Univ., Taiwan)
Page	pp. 557 - 558
Detailed information (abstract, keywords, etc)

D2-4 (Time: 11:22 - 11:36)

Title	A Progressive Mixing 20GHz ILFD with Wide Locking Range for Higher Division Ratios
Author	*Ahmed Musa, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 559 - 560
Detailed information (abstract, keywords, etc)

D2-5 (Time: 11:36 - 11:50)

Title	A 16-Gb/s Area-Efficient LD Driver with Interwoven Inductor in a 0.18-µm CMOS
Author	*Takeshi Kuboki (Kyoto Univ., Japan), Yusuke Ohtomo (NTT, Japan), Akira Tsuchiya (Kyoto Univ., Japan), Keiji Kishine (Univ. of Shiga Prefecture, Japan), Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 561 - 562
Detailed information (abstract, keywords, etc)

D2-6 (Time: 11:50 - 12:04)

Title	A PVT-robust Feedback Class-C VCO Using an Oscillation Swing Enhancement Technique
Author	*Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 563 - 564
Detailed information (abstract, keywords, etc)

D2-7 (Time: 12:04 - 12:18)

Title	A Single-Routing Layered LDPC Decoder for 10Gbase-T Ethernet in 130nm CMOS
Author	*Dan Bao, Xubin Chen, Yuebin Huang, Chuan Wu, Yun Chen, Xiao Yang Zeng (Fudan Univ., China)
Page	pp. 565 - 566
Detailed information (abstract, keywords, etc)

Session 7A System-Level Modeling, Simulation, and Verification
Time: 10:40 - 12:20 Thursday, February 2, 2012
Location: Room 204B
Chairs: Lovic Gauthier (Kyushu Univ., Japan), Alan Su (Synopsys, Taiwan)

7A-1 (Time: 10:40 - 11:05)

Title	Automatic Timing Granularity Adjustment for Host-Compiled Software Simulation
Author	Parisa Razaghi, *Andreas Gerstlauer (Univ. of Texas, Austin, U.S.A.)
Page	pp. 567 - 572
Detailed information (abstract, keywords, etc)

7A-2 (Time: 11:05 - 11:30)

Title	Performance Estimation of Embedded Software with Confidence Levels
Author	*Marco Lattuada, Fabrizio Ferrandi (Politecnico di Milano, Italy)
Page	pp. 573 - 578
Detailed information (abstract, keywords, etc)

7A-3 (Time: 11:30 - 11:55)

Title	Verifying Dynamic Power Management Schemes Using Statistical Model Checking
Author	Jayanand Asok Kumar, *Shobha Vasudevan (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 579 - 584
Detailed information (abstract, keywords, etc)

7A-4 (Time: 11:55 - 12:20)

Title	Formal Methods for Coverage Analysis of Architectural Power States in Power-Managed Designs
Author	*Aritra Hazra, Pallab Dasgupta (Indian Inst. of Tech. Kharagpur, India), Ansuman Banerjee (Indian Statistical Institute Kolkata, India), Kevin Harer (Synopsys Inc., U.S.A.)
Page	pp. 585 - 590
Detailed information (abstract, keywords, etc)

Session 7B Timing, Thermal, and Power Issues in High-Performance Design
Time: 10:40 - 12:20 Thursday, February 2, 2012
Location: Room 203
Chairs: Yuchun Ma (Tsinghua Univ., China), Masanori Hashimoto (Osaka Univ., Japan)

7B-1 (Time: 10:40 - 11:05)

Title	The Impact of Hot Carriers on Timing in Large Circuits
Author	Jianxin Fang, *Sachin Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 591 - 596
Detailed information (abstract, keywords, etc)

7B-2 (Time: 11:05 - 11:30)

Title	A Learning-Based Autoregressive Model for Fast Transient Thermal Analysis of Chip-Multiprocessors
Author	*Da-Cheng Juan, Huapeng Zhou, Diana Marculescu, Xin Li (Carnegie Mellon Univ., U.S.A.)
Page	pp. 597 - 602
Detailed information (abstract, keywords, etc)

7B-3 (Time: 11:30 - 11:55)

Title	On-Chip Statistical Hot-Spot Estimation Using Mixed-Mesh Statistical Polynomial Expression Generating and Skew-Normal Based Moment Matching Techniques
Author	Pei-Yu Huang, Yu-Min Lee, *Chi-Wen Pan (National Chiao Tung Univ., Taiwan)
Page	pp. 603 - 608
Detailed information (abstract, keywords, etc)

7B-4 (Time: 11:55 - 12:20)

Title	Design Techniques for Functional-Unit Power Gating in the Ultra-Low-Voltage Region
Author	*Michael B. Henry, Leyla Nazhandali (Virginia Tech, U.S.A.)
Page	pp. 609 - 614
Detailed information (abstract, keywords, etc)

Session 7C Interconnect, Cooling, and Charge Storage Technologies
Time: 10:40 - 12:20 Thursday, February 2, 2012
Location: Room 202
Chairs: Wei Zhang (Nanyang Technological Univ., Singapore), Hai Zhou (Northwestern Univ., U.S.A.)

7C-1 (Time: 10:40 - 11:05)

Title	Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems
Author	Yan Zheng (Tsinghua Univ., China), *Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani (Univ. of California, Santa Barbara, U.S.A.), Shiyuan Yang (Tsinghua Univ., China), Kwang-Ting Tim Cheng (Univ. of California, Santa Barbara, U.S.A.)
Page	pp. 615 - 620
Detailed information (abstract, keywords, etc)

7C-2 (Time: 11:05 - 11:30)

Title	GLOW: A Global Router for Low-Power Thermal-reliable Interconnect Synthesis using Photonic Wavelength Multiplexing
Author	Duo Ding, Bei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 621 - 626
Detailed information (abstract, keywords, etc)

7C-3 (Time: 11:30 - 11:55)

Title	Charge Replacement in Hybrid Electrical Energy Storage Systems
Author	Qing Xie, Yanzhi Wang (Univ. of Southern California, U.S.A.), Younghyun Kim, Donghwa Shin, *Naehyuck Chang (Seoul National Univ., Republic of Korea), Massoud Pedram (Univ. of Southern California, U.S.A.)
Page	pp. 627 - 632
Detailed information (abstract, keywords, etc)

7C-4 (Time: 11:55 - 12:20)

Title	Prospects of Active Cooling with Integrated Super-Lattice based Thin-Film Thermoelectric Devices for Mitigating Hotspot Challenges in Microprocessors
Author	Borislav Alexandrov, Owen Sullivan, Satish Kumar, *Saibal Mukhopadhyay (Georgia Tech, U.S.A.)
Page	pp. 633 - 638
Detailed information (abstract, keywords, etc)

Session S8 Special Session 8: Design for Reconfigurability and Adaptivity: Device, Circuit and System Perspectives
Time: 14:00 - 15:40 Thursday, February 2, 2012
Location: Room 204A
Chairs: Yiyu Shi (Missouri Univ. of Science and Tech., U.S.A.), Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)

S8-1 (Time: 14:00 - 14:25)

Title	(Invited Paper) Nano-Electro-Mechanical (NEM) Relays and their Application to FPGA Routing
Author	Chen Chen, Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee, Roger T. Howe, H.S. Philip Wong, *Subhasish Mitra (Stanford Univ., U.S.A.)
Page	p. 639
Detailed information (abstract, keywords, etc)

S8-2 (Time: 14:25 - 14:50)

Title	(Invited Paper) Capturing the Phantom of the Power Grid – On the Runtime Adaptive Techniques for Noise Reduction
Author	Tao Wang (Missouri Univ. of Science and Tech., U.S.A.), Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai (Industrial Technology Research Institute, Hsin-Chu, Taiwan), *Yiyu Shi (Missouri Univ. of Science and Tech., U.S.A.)
Page	pp. 640 - 645
Detailed information (abstract, keywords, etc)

S8-3 (Time: 14:50 - 15:15)

Title	(Invited Paper) Post Silicon Skew Tuning: Survey and Analysis
Author	Mac Y.C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, *Shih-Chieh Chang (NTHU, Taiwan)
Page	pp. 646 - 651
Detailed information (abstract, keywords, etc)

S8-4 (Time: 15:15 - 15:40)

Title	(Invited Paper) Compilation and Architecture Support for Customized Vector Instruction Extension
Author	*Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, Marco Vitanza (Univ. of California, Los Angeles, U.S.A.)
Page	pp. 652 - 657
Detailed information (abstract, keywords, etc)

Session 8A Scheduling for Embedded and High-Performance Systems
Time: 14:00 - 15:40 Thursday, February 2, 2012
Location: Room 204B
Chairs: Chun Jason Xue (City Univ. of Hong Kong), Morteza Biglari-Abhari (Univ. of Auckland)

8A-1 (Time: 14:00 - 14:25)

Title	Thread Affinity Mapping for Irregular Data Access on Shared Cache GPGPU
Author	*Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Page	pp. 659 - 664
Detailed information (abstract, keywords, etc)

8A-2 (Time: 14:25 - 14:50)

Title	Modular Scheduling of Distributed Heterogeneous Time-Triggered Automotive Systems
Author	*Martin Lukasiewycz (TUM CREATE Centre for Electromobility, Singapore), Dip Goswami, Reinhard Schneider, Samarjit Chakraborty (Tech. Univ. of Munich, Germany)
Page	pp. 665 - 670
Detailed information (abstract, keywords, etc)

8A-3 (Time: 14:50 - 15:15)

Title	RAISE: Reliability-Aware Instruction SchEduling for Unreliable Hardware
Author	Semeen Rehman, Muhammad Shafique, Florian Kriebel, *Jörg Henkel (Karlsruhe Inst. of Tech. (KIT), Germany)
Page	pp. 671 - 676
Detailed information (abstract, keywords, etc)

8A-4 (Time: 15:15 - 15:40)

Title	On-Line Leakage-Aware Energy Minimization Scheduling for Hard Real-Time Systems
Author	Huang Huang, Ming Fan, *Gang Quan (Florida International Univ., U.S.A.)
Page	pp. 677 - 682
Detailed information (abstract, keywords, etc)

Session 8B Automated Debugging and Validation
Time: 14:00 - 15:40 Thursday, February 2, 2012
Location: Room 203
Chairs: Jiun-Lang Huang (National Taiwan Univ., Taiwan), Jai-Ming Lin (National Cheng Kung Univ., Taiwan)

8B-1 (Time: 14:00 - 14:25)

Title	A Formal Approach to Debug Polynomial Datapath Designs
Author	*Bijan Alizadeh (Univ. of Tehran, Iran)
Page	pp. 683 - 688
Detailed information (abstract, keywords, etc)

8B-2 (Time: 14:25 - 14:50)

Title	Automated Debugging of Counterexamples in Formal Verification of Pipelined Microprocessors
Author	*Miroslav N. Velev, Ping Gao (Aries Design Automation, U.S.A.)
Page	pp. 689 - 694
Detailed information (abstract, keywords, etc)

8B-3 (Time: 14:50 - 15:15)

Title	On Error Tolerance and Engineering Change with Partially Programmable Circuits
Author	Hratch Mangassarian (Univ. of Toronto, Canada), Hiroaki Yoshida (Univ. of Tokyo, Japan), Andreas Veneris (Univ. of Toronto, Canada), Shigeru Yamashita (Ritsumeikan Univ., Japan), *Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 695 - 700
Detailed information (abstract, keywords, etc)

8B-4 (Time: 15:15 - 15:40)

Title	On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation
Author	Ming Gao, *Peter Lisherness (Univ. of California, Santa Barbara, U.S.A.), Jing-Jia Liou (National Tsing Hua Univ., Taiwan), Kwang-Ting (Tim) Cheng (Univ. of California, Santa Barbara, U.S.A.)
Page	pp. 701 - 706
Detailed information (abstract, keywords, etc)

Session 8C DFM for Nanolithography
Time: 14:00 - 15:40 Thursday, February 2, 2012
Location: Room 202
Chairs: David Z. Pan (Univ. of Texas, Austin, U.S.A.), C.-K. Cheng (Univ. of California, San Diego, U.S.A.)

8C-1 (Time: 14:00 - 14:25)

Title	Hybrid Lithography Optimization with E-Beam and Immersion Processes for 16nm 1D Gridded Design
Author	Yuelin Du, Hongbo Zhang, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.)
Page	pp. 707 - 712
Detailed information (abstract, keywords, etc)

8C-2 (Time: 14:25 - 14:50)

Title	Design-Patterning Co-optimization of SRAM Robustness for Double Patterning Lithography
Author	Vivek Joshi (GLOBALFOUNDRIES, U.S.A.), *Dennis Sylvester (Univ. of Michigan, U.S.A.), Kanak Agarwal (IBM Research, U.S.A.)
Page	pp. 713 - 718
Detailed information (abstract, keywords, etc)

8C-3 (Time: 14:50 - 15:15)

Title	Efficient Pattern Relocation for EUV Blank Defect Mitigation
Author	Hongbo Zhang, Yuelin Du, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Rasit O. Topalaglu (GLOBALFOUNDRIES, U.S.A.)
Page	pp. 719 - 724
Detailed information (abstract, keywords, etc)

8C-4 (Time: 15:15 - 15:40)

Title	Character Design and Stamp Algorithms for Character Projection Electron-Beam Lithography
Author	Peng Du, Wenbo Zhao, Shih-Hung Weng, *Chung-Kuan Cheng, Ronald Graham (Univ. of California, San Diego, U.S.A.)
Page	pp. 725 - 730
Detailed information (abstract, keywords, etc)

Session S9 Special Session 9: Quality Assurance for 3D-Stacked ICs
Time: 16:10 - 17:50 Thursday, February 2, 2012
Location: Room 204A
Chair: Tai-Chen Chen (National Central Univ., Taiwan)

S9-1 (Time: 16:10 - 16:35)

Title	(Invited Paper) Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges
Author	*Qiang Xu, Li Jiang (Chinese Univ. of Hong Kong, Hong Kong), Huiyun Li (Shenzhen Institutes of Advanced Technology, China), Bill Eklow (Cisco Systems, U.S.A.)
Page	pp. 731 - 737
Detailed information (abstract, keywords, etc)

S9-2 (Time: 16:35 - 17:00)

Title	(Invited Paper) Yield-Aware Time-Efficient Testing and Self-fixing Design for TSV-Based 3D ICs
Author	*Jing Xie, Yu Wang, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Page	pp. 738 - 743
Detailed information (abstract, keywords, etc)

S9-3 (Time: 17:00 - 17:25)

Title	(Invited Paper) On Test and Repair of 3D Random Access Memory
Author	Cheng-Wen Wu (National Tsing Hua Univ., Taiwan), *Shyue-Kun Lu (National Taiwan Univ. of Science and Tech., Taiwan), Jin-Fu Li (National Central Univ., Taiwan)
Page	pp. 744 - 749
Detailed information (abstract, keywords, etc)

S9-4 (Time: 17:25 - 17:50)

Title	(Invited Paper) Design for Manufacturability and Reliability for TSV-based 3D-ICs
Author	*David Z. Pan (Univ. of Texas, Austin, U.S.A.), Sung Kyu Lim, Krit Athikulwongse, Moongon Jung (Georgia Tech, U.S.A.), Joydeep Mitra, Jiwoo Pak (Univ. of Texas, Austin, U.S.A.), Mohit Pathak (Georgia Tech, U.S.A.), Jae-seok Yang (Univ. of Texas, Austin, U.S.A.)
Page	pp. 750 - 755
Detailed information (abstract, keywords, etc)

Session 9A Design for System Reliability
Time: 16:10 - 17:50 Thursday, February 2, 2012
Location: Room 204B
Chairs: Naehyuck Chang (Seoul National Univ., Republic of Korea), Shih-Hao Hung (National Taiwan Univ., Taiwan)

9A-1 (Time: 16:10 - 16:35)

Title	The Synthesis of Linear Finite State Machine-Based Stochastic Computational Elements
Author	*Peng Li (Univ. of Minnesota, U.S.A.), Weikang Qian (Univ. of Michigan-Shanghai Jiao Tong Univ. Joint Institute, China), Marc D. Riedel, Kia Bazargan, David J. Lilja (Univ. of Minnesota, U.S.A.)
Page	pp. 757 - 762
Detailed information (abstract, keywords, etc)

9A-2 (Time: 16:35 - 17:00)

Title	Selective Time Borrowing for DSP Pipelines with Hybrid Voltage Control Loop
Author	*Paul N. Whatmough (Univ. College London, U.K.), Shidhartha Das, David M. Bull (ARM Ltd., U.K.), Izzat Darwazeh (Univ. College London, U.K.)
Page	pp. 763 - 768
Detailed information (abstract, keywords, etc)

9A-3 (Time: 17:00 - 17:25)

Title	EPROF: An Energy/Performance/Reliability Optimization Framework for Streaming Applications
Author	*Yavuz Yetim, Sharad Malik, Margaret Martonosi (Princeton Univ., U.S.A.)
Page	pp. 769 - 774
Detailed information (abstract, keywords, etc)

Session 9B Logic and Datapath Synthesis
Time: 16:10 - 17:50 Thursday, February 2, 2012
Location: Room 203
Chairs: Robert Wille (Univ. of Bremen, Germany), Yuichi Nakamura (NEC, Japan)

9B-1 (Time: 16:10 - 16:35)

Title	BTI-Aware Design Using Variable Latency Units
Author	*Saket Gupta, Sachin Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 775 - 780
Detailed information (abstract, keywords, etc)

9B-2 (Time: 16:35 - 17:00)

Title	Linear Decomposition of Index Generation Functions
Author	*Tsutomu Sasao (Kyushu Inst. of Tech., Japan)
Page	pp. 781 - 788
Detailed information (abstract, keywords, etc)

9B-3 (Time: 17:00 - 17:25)

Title	Fixed-Point Accuracy Analysis of Datapaths with Mixed CORDIC and Polynomial Computations
Author	*Omid Sarbishei, Katarzyna Radecka (McGill Univ., Canada)
Page	pp. 789 - 794
Detailed information (abstract, keywords, etc)

9B-4 (Time: 17:25 - 17:50)

Title	Algorithm for Synthesizing Design Context-Aware Fast Carry-Skip Adders
Author	*Kiyoung Kim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 795 - 800
Detailed information (abstract, keywords, etc)

Session 9C Video, Display, and Signal Processing Technologies and Techniques
Time: 16:10 - 17:50 Thursday, February 2, 2012
Location: Room 202
Chairs: Shao-Yi Chien (National Taiwan Univ., Taiwan), Yen-Kuang Chen (Intel Corp., U.S.A.)

9C-1 (Time: 16:10 - 16:35)

Title	A 16-pixel Parallel Architecture with Block-level/Mode-level Co-reordering Approach for Intra Prediction in 4kx2k H.264/AVC Video Encoder
Author	Huailu Ren (Shandong Univ. of Science and Tech., China), *Yibo Fan (Fudan Univ., China), Xinhua Chen (Shandong Univ. of Science and Tech., China), Xiaoyang Zeng (Fudan Univ., China)
Page	pp. 801 - 806
Detailed information (abstract, keywords, etc)

9C-2 (Time: 16:35 - 17:00)

Title	Fine-grained Dynamic Voltage Scaling on OLED Display
Author	Xiang Chen, Jian Zheng, *Yiran Chen (Univ. of Pittsburgh, U.S.A.), Hai Li (Polytechnic Inst. of New York Univ., U.S.A.), Wei Zhang (Nanyang Technological Univ., Singapore)
Page	pp. 807 - 812
Detailed information (abstract, keywords, etc)

9C-3 (Time: 17:00 - 17:25)

Title	A Reconfigurable Accelerator for Neuromorphic Object Recognition
Author	Jagdish Sabarad, Srinidhi Kestur, Mi Sun Park, Dharav Dantara, *Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.), Yang Chen, Deepak Khosla (HRL Laboratories, U.S.A.)
Page	pp. 813 - 818
Detailed information (abstract, keywords, etc)

9C-4 (Time: 17:25 - 17:50)

Title	Efficient Implementation of Multi-Moduli Architectures for Binary-to RNS Conversion
Author	*Hector Pettenghi (Instituto de Engenharia de Sistemas e Computadores (INESC-ID), Portugal), Leonel Sousa (Instituto Superior Tecnico (IST)/ Instituto de Engenharia de Sistemas e Computadores (INESC-ID), Portugal), Jude Angelo Ambrose (Univ. of New South Wales, Australia)
Page	pp. 819 - 824
Detailed information (abstract, keywords, etc)

The 17th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of Papers

The 17th Asia and South Pacific Design Automation Conference
Technical Program