Technical Program Committee

Technical Program Chair

Yao-Wen Chang (National Taiwan University, Taiwan)

Technical Program Vice Chair

Yuan Xie (Penn State University, U.S.A.)

Hui Guo (University of New South Wales, Australia)

Secretary

Jiun-Lang Huang (National Taiwan University, Taiwan)

Ric Chung-Yang Huang (National Taiwan University, Taiwan)

Sub committees and sub committee chairs

* : subcommittee chairs
[01] System-Level Modeling and Simulation/Verification
* Chia-Lin Yang (National Taiwan University, Taiwan)
Derek Chiou (University of Texas at Austin, U.S.A.)
Lovic Gauthier (Kyushu University, Japan)
Juinn-Dar Huang (National Chiao Tung University, Taiwan)
Byeong Min (Samsung, Korea)
Alan Su (Synopsys, U.S.A.)
[02] System-Level Synthesis and Optimization
* Kiyoung Choi (Seoul National Univ., Korea)
Eui Young Chung (Yonsei Univ., Korea)
Aseem Gupta (Freescale, U.S.A.)
Pao-Ann Hsiung (National Chung Cheng Univ., Taiwan)
Tsuyoshi Isshiki (Tokyo Inst. of Tech., Japan)
Yun (Eric) Liang (Advanced Digital Sciences Center (ADSC), Singapore)
Masanori Muroyama (Tohoku Univ., Japan)
[03] System-Level Memory/Communication Design and Networks on Chip
* David Atienza (EPFL, Switzerland)
Fabien Clermidy (CEA-LETI, France)
Ali Irturk (UCSD, U.S.A.)
Michihiro Koibuchi (NII, Japan)
Hsien-Hsin Lee (GIT, U.S.A.)
Fernando Gehm Moraes (PUCRS, Brazil)
Sri Parameswaran (Univ. of New South Wales, Australia)
Yoshinori Takeuchi (Osaka Univ., Japan)
Yu Wang (Tsinghua Univ., China)
[04] Embedded and Real-Time Systems
* Tei-Wei Kuo (National Taiwan University, Taiwan)
Jian-Jia Chen (Karlsruhe Inst. of Tech., Germany)
Yiran Chen (University of Pittsburgh, U.S.A.)
Nikil Dutt (UC Irvine, U.S.A.)
Qingxu Deng (Northeastern University, China)
Bernhard Egger (Seoul National University, Korea)
Pi-Cheng Hsiu (Academia Sinica, Taiwan)
Hiroki Matsutani (Keio University, Japan)
Zili Shao (Hong Kong Polytechnic Univ., Hong Kong)
Yibo Xue (Tsinghua Univ., China)
[05] High-Level/Behavioral/Logic Synthesis and Optimization
* NagisaIshiura (KwanseiGakuin Univ., Japan)
Yuko Hara-Azumi (Ritsumeikan Univ., Japan)
Yajun Ha (National Univ. of Singapore, Singapore)
Roland Jie-Hong Jiang (National Taiwan University, Taiwan)
Kazuyoshi Takagi (Kyoto Univ., Japan)
Chun-Yao Wang (National Tsing-Hua Univ., Taiwan)
Robert Wille (Univ. of Bremen, Germany)
Shigeru Yamashita (Ritsumeikan Univ., Japan)
[06] Validation and Verification for Behavioral/Logic Design
* Masahiro Fujita (University of Tokyo, Japan)
Görschwin Fey (University of Bremen, Germany)
Hui-Ru Jiang (National Chiao-Tung University, Taiwan)
In-Mo Moon (Synopsys, U.S.A.)
Virendra Singh (Indian Institute of Science, India)
Miroslav Velev (Aries Design Automation, U.S.A.)
Yoshinori Watanabe (Cadence, U.S.A.)
[07] Physical Design
* Gi-Joon Nam (IBM Research, U.S.A.)
Sheqin Dong (Tsinghua University, China)
Susmita Sur-Kolay (Indian Statistical Institute, India)
Yih-Lang Li (National Chiao-Tung University, Taiwan)
Cliff Sze (IBM Research, U.S.A.)
Hsiao-Ping Tseng (Magma Design Automation, U.S.A.)
Yasuhiro Takashima (University of Kitakyushu, Japan)
Lingli Wang (Fudan University, China)
Hai Zhou (Northwestern University, U.S.A.)
[08] Timing, Power Thermal Analysis and Optimization
* Sachin Sapatnekar (University of Minnesota, U.S.A.)
Lih-Yih Chiou (National Cheng Kung University, Taiwan)
Mango Chia-Tso Chao (National Chiao-Tung University, Taiwan)
Azadeh Davoodi (University of Wisconsin, U.S.A.)
Masanori Hashimoto (Osaka University, Japan)
Bong-Hyun Lee (Samsung, Korea)
Yuchun Ma (Tsinghua University, China)
Seungwhun Paik (KAIST, Korea)
Kimiyoshi Usami (Shibaura Institute of Technology, Japan)
[09] Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation
* Youngsoo Shin (KAIST, Korea)
Ram Achar (Carleton Univ., Canada)
Jung Yun Choi (Samsung, Korea)
Ken Choi (Illinois Inst. of Tech., U.S.A.)
Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Ngai Wong (Univ. of Hong Kong, Hong Kong)
[10] Design for Manufacturability/Yield and Statistical Design
* David Pan (University of Texas at Austin, U.S.A.)
Steven (Chien-Wen) Chen (TSMC, Taiwan)
Kartik Mohanram (Rice Univ., U.S.A.)
Murakata Masami (Toshiba, Japan)
Srinivas Raghvendra (Synopsys, U.S.A.)
Zheng Shi (Zhejiang Univ., China)
[11] Test and Design for Testability
* Shi-Yu Huang (National Tsing-Hua University, Taiwan)
Wu-Tung Cheng (Mentor Graphics, U.S.A.)
Jiun-Lang Huang (National Taiwan Univ., Taiwan)
Xiaowei Li (Chinese Academy of Science, China)
Michel Renovell (LIRMM CNRS, France)
Tomokazu Yoneda (NAIST, Japan)
[12] Analog, RF and Mixed Signal Design and CAD
* Sheldon Tan (University of California at Riverside, U.S.A.)
Hideki ASAI (Shizuoka University, Japan)
Yici Cai (Tsinghua University, China)
Jai-Ming Lin (National Cheng Kung University, Taiwan)
Hao Yu (Nanyang Technological Univ., Singapore)
[13] Emerging Technologies and Applications
* Cheng-Kok Koh (Purdue University, U.S.A.)
Tsung-Yi Ho (National Cheng-Kung Univ., Taiwan)
Jente B. Kuang (IBM Research, U.S.A.)
Hai (Helen) Li (Polytechnic Institute of New York Univ., U.S.A.)
Sung-Kyu Lim (Georgia Tech, U.S.A.)
Jongsun Park (Korea University, Korea)
Wei Zhang (Nanyang Technological Univ., Singapore)

Last Updated on: 11 8, 2011