Special Sessions


S1: Robust and Resilient Designs from the Bottom Up: Technology, CAD, Circuit and System Issues
Tuesday, January 31, 14:00-15:40

  • S1-1: Vijay J. Reddi, David Z. Pan (Univ. of Texas, Austin, U.S.A.), Sani Nassif (IBM, U.S.A.), Keith A. Bowman (Intel, U.S.A.) "Robust and Resilient Designs from the Bottom-Up: Technology, CAD, Circuit, and System Issues"
  • S1-2: Sani Nassif (IBM, U.S.A.) "Technology Challenges beyond 22nm"
  • S1-3: David Z. Pan (Univ. of Texas, Austin, U.S.A.) "Physical CAD for Robust Designs"
  • S1-4: Keith A. Bowman (Intel, U.S.A.) "Resilient Circuit Design Trade-Offs for Improving Performance & Energy Efficiency"
  • S1-5: Vijay J. Reddi (Univ. of Texas, Austin, U.S.A.) "Coordinated System Design for Resiliency"

S2: Domain Specific Accelerators
Tuesday, January 31, 16:10-17:50

  • S2-1: Mike O'Connor (AMD, U.S.A.) "Accelerated Processing and The Fusion System Architecture"
  • S2-2: Alex Bui, Jason Cong, Luminita Vese, Bo Yuan, Yi Zou (UCLA, U.S.A), Kwang-Ting Cheng, Yi-Chu Wang (UCSB, U.S.A.) "Platform Characterization for Domain-Specific Computing"
  • S2-3: Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng, Vikram Bhatt, Joe Auricchio, Steven Swanson, Michael Bedford Taylor (UCSD, U.S.A.) "GreenDroid: An Architecture for the Dark Silicon Age"
  • S2-4: Ravi Iyer (Intel, U.S.A.) "Accelerator-Rich Architectures: Implications, Opportunities and Challenges"
  • S2-5: Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan (Penn State, U.S.A.)

S3: Design and Prototyping of Invasive MPSoC Architectures
Wednesday, February 1, 10:40-12:20

  • S3-1: Sascha Roloff, Frank Hannig, Jürgen Teich (Univ. of Erlangen-Nuremberg, Germany) "Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs"
  • S3-2: Jorg Henkel (Karlsruhe Inst. of Tech., Germany), Andreas Herkersdorf (Tech. Univ. of Munich, Germany), Lars Bauer (Karlsruhe Inst. of Tech., Germany), Thomas Wild (Tech. Univ. of Munich, Germany), Michael Hubner (Karlsruhe Inst. of Tech., Germany), Ravi Kumar Pujari (Tech. Univ. of Munich, Germany), Artjom Grudnitsky, Jan Heisswolf (Karlsruhe Inst. of Tech., Germany), Aurang Zaib (Tech. Univ. of Munich, Germany), Benjamin Vogel (Karlsruhe Inst. of Tech., Germany), Vahid Lari (Univ. of Erlangen-Nuremberg, Germany), Sebastian Kobbe (Karlsruhe Inst. of Tech., Germany) "Invasive Manycore Architectures"
  • S3-3: Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig (Karlsruhe Inst. of Tech., Germany), David May (Technische Univ. München, Germany)"Hardware Prototyping of Novel Invasive Multicore Architectures"
  • S3-4: Johny Paul, Walter Stechele (Tech. Univ. of Munich, Germany), M. Krohnert, T. Asfour, R. Dillmann (Karlsruhe Inst. of Tech., Germany) (Univ. of Texas, Austin, U.S.A.) "Invasive Computing for Robotic Vision"

S4: Making ESL Models Work
Wednesday, February 1, 10:40-12:20

  • S4-1: "Abstract System-Level Models for Early Performance and Power Exploration"
  • S4-2: "Virtual Prototyping of Cyber Physical Systems"
  • S4-3: Rainer Dömer, Weiwei Chen, Xu Han (UC Irvine, U.S.A.) "Parallel Discrete Event Simulation of Transaction Level Models"
  • S4-4: Masahiro Fujita, Hiroaki Yoshida (U. Tokyo, Japan) "Post-Silicon Patching for Verification/Debugging with High-Level Models and Programmable Logic"

S5: Advanced Post-silicon Validation and Debugging Techniques for SoC
Wednesday, February 1, 14:00-15:40

  • S5-1: Subhasish Mitra, David Lin (Stanford U., U.S.A.), Nagib Hakim, Don Gardner (Intel, U.S.A.)"Bug Localization Techniques for Effective Post-Silicon Validation"
  • S5-2: Peter Lisherness, Kwang-Ting Cheng (UCSB, U.S.A.) "Improving Validation Coverage Metrics to Account for Limited Observability"
  • S5-3: Yu-Shen Yang (Vennsa Tech., Canada), Andreas Veneris (U. Toronto, Canada), Nicola Nicolici (McMaster U., Canada), Masahiro Fujita (U. Tokyo, Japan) "Automated Data Analysis Techniques for a Modern Silicon Debug Environment"
  • S5-4: Amir Nahir, Avi Ziv (IBM, Israel), Subrat Panda (IBM, India)"Optimizing Test-Generation to the Execution Platform"

S6: Design and Architecture of Emerging Non-volatile Memory Technologies
Wednesday, February 1, 14:00-15:40

  • S6-1: Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan (Penn. State, U.S.A.) "When to forget: A system-level perspective on STT-RAMs"
  • S6-2: Tianzheng Wang, Duo Liu, Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Chengmo Yang (Univ. of Delaware, U.S.A.) "Write-Activity-Aware Page Table Management for PCM-based Embedded Systems"
  • S6-3: Yiran Chen, Yaojun Zhang, Peiyuan Wang (U. Pittsburgh, U.S.A.)"Probabilistic Design in Spintronic Memory and Logic Circuit"
  • S6-4: Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen (National Tsing Hua Uni., Taiwan), Hiroyuki Yamauchi (FIT, Japan), Pi-Feng Chiu, Shyh-Shyuan Sheu (ITRI, Taiwan) "Endurance-Aware Circuit Designs of Nonvolatile Logic and Nonvolatile SRAM Using Resistive Memory (Memristor) Device"

S7: Sensor Node Optimization in Machine-to-Machine (M2M) Networks
Wednesday, February 1, 16:10-17:50

  • S7-1: Yen-Kuang Chen (Intel, U.S.A.), "Challenges and Opportunities of Internet of Things"
  • S7-2: Wei Liu, Xiaotian Fei, Tao Tang, Pengjun Wang, Hong Luo, Beixing Deng, Huazhong Yang (Tsinghua Uni., China) "Application Specific Sensor Node Architecture Optimization --- Experiences from Field Deployments"
  • S7-3: Shih-Hao Hung, Tei-Wei Kuo, Chi-Sheng Shih, Chia-Heng Tu (NTU, Taiwan) "System-Wide Profiling and Optimization with Virtual Machines"
  • S7-4: Shao-Yi Chien, Teng-Yuan Cheng, Chieh-Chuan Chiu, Pei-Kuei Tsung (NTU, Taiwan), Chia-han Lee (Acad. Sinica, Taiwan), V. Srinivasa Somayazulu, Yen-Kuang Chen (Intel, U.S.A.) "Power Optimization ofWireless Video Sensor Nodes in M2M Network"

S8: Design for Reconfigurability and Adaptivity: Device, Circuit and System Perspectives
Thursday, February 2, 14:00-15:40

  • S8-1: Chen Chen, Scott Lee, J Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra (Stanford U., U.S.A.) "Nano-Electro-Mechanical (NEM) Relays and their Application to FPGA Routing"
  • S8-2: Tao Wang (MST, U.S.A.), Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai (ITRI, Taiwan), Yiyu Shi (MST, U.S.A.) "Capturing the Phantom of the Power Grid – On the Runtime Adaptive Techniques for Noise Reduction"
  • S8-3: Yu-Chien Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang (NTHU, Taiwan) "Post Silicon Skew Tuning: Survey and Analysis"
  • S8-4: Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman (UCLA, U.S.A.)"Architecture and Compilation Support for Custom Vector Instructions"

S9: Quality Insurance for 3D-Stacked ICs
Thursday, February 2, 16:10-17:50

  • S9-1: Qiang Xu, Li Jiang (Chinese Univ. of Hong Kong, Hong Kong), Huiyun Li (Shenzhen Institutes of Advanced Technology, China), Bill Eklow (Cisco Systems, Hong Kong) "Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges"
  • S9-2: Jing Xie, Yuan Xie (Pennsylvania State Univ., U.S.A.) "Yield-Aware Time-Efficient Testing and Self-fixing Design for TSV-Based 3D ICs"
  • S9-3: Cheng-Wen Wu (National Tsing-Hua Univ., Taiwan), Shyue-Kun Lu (National Taiwan Univ. of Science Technology, Taiwan), Jin-Fu Li (National Central Univ., Taiwan) "On Test and Repair of 3D Random Access Memory"
  • S9-4: David Z. Pan (Univ. of Texas, Austin, U.S.A.), Sung Kyu Lim, Krit Athikulwongse, Moongon Jung (Georgia Tech, U.S.A.), Joydeep Mitra, Jiwoo Pak (Univ. of Texas, Austin, U.S.A.), Mohit Pathak (Georgia Tech, U.S.A.), Jae-seok Yang (Univ. of Texas, Austin, U.S.A.) "Design for Manufacturability and Reliability for TSV-based 3D-ICs"

Last Updated on: January 24 2012