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The 18th Asia and South Pacific Design Automation Conference

Session 2A  Special Session: Dependability of on-Chip Systems
Time: 13:40 - 15:40 Wednesday, January 23, 2013
Organizer: Jörg Henkel (Karlsruhe Institute of Technology, Germany)

2A-1 (Time: 13:40 - 14:20)
Title(Invited Paper) Thermal Management for Dependable on-chip Systems
Author*Jörg Henkel, Thomas Ebi, Hussam Amrouch, Heba Khdr (Karlsruhe Institute of Technology, Germany)
Pagepp. 113 - 118
KeywordDependability, Thermal Management, Aging
AbstractDependability has become a growing concern in the nano-CMOS era due to elevated temperatures and an increased susceptibility to temperature of the small structures. We present an overview of temperature-related effects that threaten dependability and a methodology for reducing the dependability concerns through thermal management utilizing the concept of aging budgeting.

2A-2 (Time: 14:20 - 15:00)
Title(Invited Paper) Dependable VLSI Platform using Robust Fabrics
Author*Hidetoshi Onodera (Kyoto University, Japan)
Pagepp. 119 - 124
Keyworddependable VLSI, DFM, variability, soft error, aging
AbstractExtreme scaling imposes enormous challenges on LSI design such as manufacturability degradation, variability increase, performance aging, and soft-error vulnerability. For overcoming these difficulties, we have been developing a VLSI platform that can realize dependable circuits with required level of reliability. The platform project tackles the challenges with collaborative researches on layout, circuit, architecture, and design automation. Overview of the project as well as key achievements on the component-level and the architecture-level will be explained, followed by a brief introduction of the platform SoC and its C-based design tools.

2A-3 (Time: 15:00 - 15:40)
Title(Invited Paper) Variability-Aware Memory Management for Nanoscale Computing
Author*Nikil Dutt (University of California, Irvine, U.S.A.), Puneet Gupta (University of California, Los Angeles, U.S.A.), Alex Nicolau, Luis Angel D. Bathen (University of California, Irvine, U.S.A.), Mark Gottscho (University of California, Los Angeles, U.S.A.)
Pagepp. 125 - 132
KeywordMemory Management, Variation-Aware Design
AbstractAs the semiconductor industry continues to push the limits of sub-micron technology, the ITRS expects hardware (e.g., die-to-die, wafer-to-wafer, and chip-to-chip) variations to continue increasing over the next few decades. As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as minimize power consumption. The memory subsystem is one of the largest components in today’s computing system, a main contributor to the overall power consumption of the system, and therefore one of the most vulnerable components to the effects of variations (e.g., power). This paper discusses the concept of variability-aware memory management for nanoscale computing systems. We show how to opportunistically exploit the hardware variations in on- chip and off-chip memory at the system level through the deploy- ment of variation-aware software stacks.