| Title | Optimal Partition with Block-Level Parallelization in C-to-RTL Synthesis for Streaming Applications |
| Author | *Shuangchen Li, Yongpan Liu (Tsinghua University, China), X.Sharon Hu (University of Notre Dame, U.S.A.), Xinyu He, Yining Zhang (Tsinghua University, China), Pei Zhang (Y Explorations Inc., U.S.A.), Huazhong Yang (Tsinghua University, China) |
| Page | pp. 225 - 230 |
| Keyword | HLS, Partition |
| Abstract | Developing FPGA solutions for streaming applications written in C (or its variants) can benefit greatly from automatic C-to-RTL (C2RTL) synthesis. Yet, the complexity and stringent throughput/cost constraints of such applications are rather challenging for existing C2RTL synthesis tools. This paper considers automatic partition and block-level parallelization to address these challenges. An MILP-based approach is introduced for finding an optimal partition of a given program into blocks while allowing block-level parallelization. In order to handle extremely large problem instances, a heuristic algorithm is also discussed. Experimental results based on seven well known multimedia applications demonstrate the effectiveness of both solutions. |
| Slides | |
| Title | Multi-Mode Pipelined MPSoCs for Streaming Applications |
| Author | *Haris Javaid, Daniel Witono, Sri Parameswaran (University of New South Wales, Australia) |
| Page | pp. 231 - 236 |
| Keyword | Pipelined MPSoCs, Streaming Applications, Multi-mode Accelerators |
| Abstract | In this paper, we propose a design flow for the pipelined paradigm of Multi-Processor System on Chips (MPSoCs) targeting multiple streaming applications. A multi-mode pipelined MPSoC, used as a streaming accelerator, executes multiple, mutually exclusive applications through modes where each mode refers to the execution of one application. We model each application as a directed graph. The challenge is to merge application graphs into a single graph so that the multi-mode pipelined MPSoC derived from the merged graph contains minimal resources. We solve this problem by finding maximal overlap between application graphs. Three heuristics are proposed where two of them greedily merge application graphs while the third one finds an optimal merging at the cost of higher running time. The results indicate significant area saving (up to 62\% processor area, 57\% FIFO area and 44 processor/FIFO ports) with minuscule degradation of system throughput (up to 2\%) and latency (up to 2\%) and increase in energy values (up to 3\%) when compared to widely used approach of designing distinct pipelined MPSoCs for individual applications. Our work is the first step in the direction of multi-mode pipelined MPSoCs, and the results demonstrate the usefulness of resource sharing among pipelined MPSoCs based streaming accelerators in a multimedia platform. |
| Slides | |
| Title | Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis |
| Author | *Cong Hao, Song Chen, Takeshi Yoshimura (Waseda University, Japan) |
| Page | pp. 237 - 242 |
| Keyword | High-Level Synthesis, Scheduling, low-power |
| Abstract | In this work, we focus on the problem of latency-constrained scheduling with consideration of multiple voltage technologies in High-level synthesis.Without the resource concern, we propose an Integer Linear Programming (ILP) formulation, whose constraint matrix is the node-arc incidence matrix of a network graph, for power minimization. Accordingly, the formulation is relaxed to a piecewise Linear Programming problem having only integer feasible solutions and optimally solved using the efficient piecewise-linear extended network simplex method(PLNSM). The experimental results showed 80X+ speedup compared to the general linear programming formulation. Considering the resource usage, we propose a two-stage heuristic Network Simplex Method based Power-efficient Multiple Voltage Scheduling(NPMVS) method. Firstly, the above relaxed LP formulation is modified to perform mobility allocation and delay assignment for the operations so as to minimize the power and the differences between the allocated operation mobilities and the predefined target mobilities. The modified formulation is solved using the PLNSM and iteratively performed to minimize power and resource density variation in control steps by gradually updating the predefined target mobilities. Secondly, with the allocated operation mobilities, we apply dependency-free scheduling with the objective of minimizing the resource usage. Experimental results show that the proposed method can produce optimum solutions for all 6 benchmarks with 14 groups of data in a maximum time of 0.25 second. |
| Slides | |
| Title | VISA Synthesis: Variation-Aware Instruction Set Architecture Synthesis |
| Author | *Yuko Hara-Azumi (Nara Institute of Science and Technology, Japan), Takuya Azumi (Ritsumeikan University, Japan), Nikil Dutt (University of California, Irvine, U.S.A.) |
| Page | pp. 243 - 248 |
| Keyword | ISA synthesis, process variation, SSTA, timing faults |
| Abstract | We present VISA: a novel Variation-aware Instruction Set Architecture synthesis approach that makes effective use of process variation from both software and hardware points of view. To achieve an efficient speedup, VISA selects custom instructions based on statistical static timing analysis (SSTA) for aggressive clocking. Furthermore, with minimum performance overhead, VISA dynamically detects and corrects timing faults resulting from aggressive clocking of the underlying processor. This hybrid software/hardware approach brings the significant speedup without degrading the yield. Our experimental results on commonly used ISA synthesis benchmarks demonstrate that VISA achieves significant performance improvement compared with a traditional deterministic worst case-based approach (up to 78.0%) and an existing SSTA-based approach (up to 49.4%). |
| Slides | |