| Title | Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache |
| Author | Qingan Li (City University of Hong Kong, Hong Kong), Jianhua Li, Liang Shi (University of Science and Technology of China, China), *Chun Jason Xue (City University of Hong Kong, Hong Kong), Yiran Chen (University of Pittsburgh, U.S.A.), Yanxiang He (Wuhan University, China) |
| Page | pp. 273 - 278 |
| Keyword | volatile STT-RAM, refresh, compiler |
| Abstract | Recently, researchers propose to improve the efficiency of STT-RAM by relaxing its non-volatility. To avoid data loss resulting from volatility, dynamic refresh schemes are indispensable. In this paper, we propose to reduce dynamic refresh through re-arranging program data layout at compilation time. Experimental results show that, the proposed methods can reduce the number of refresh operations by 73.3%, reduce the dynamic energy consumption by 27.6%, and in the meantime slightly increase the performance by 0.7%. |
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| Title | Curling-PCM: Application-Specific Wear Leveling for Phase Change Memory based Embedded Systems |
| Author | *Duo Liu (College of Computer Science, Chongqing University, China), Tianzheng Wang (Department of Computer Science, University of Toronto, Canada), Yi Wang, Zili Shao (Department of Computing, The Hong Kong Polytechnic University, Hong Kong), Qingfeng Zhuge, Edwin Sha (College of Computer Science, Chongqing University, China) |
| Page | pp. 279 - 284 |
| Keyword | Phase chang memory, wear leveling, embedded systems, application-specific, response time |
| Abstract | Phase change memory (PCM) has been used as NOR replacement in embedded systems. However, endurance problems greatly limit its adoption in embedded systems. This paper utilizes application-specific features and proposes a wear leveling technique, Curling-PCM, which periodically moves the hot region and guarantees response time through a partial curling policy. Experimental results show effectiveness of the proposed technique. We expect this work can serve as a first step towards the utilization of application-specific features in PCM-based embedded systems. |
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| Title | Selectively Protecting Error-Correcting Code for Area-Efficient and Reliable STT-RAM Caches |
| Author | *Junwhan Ahn (Seoul National University, Republic of Korea), Sungjoo Yoo (Pohang University of Science and Technology, Republic of Korea), Kiyoung Choi (Seoul National University, Republic of Korea) |
| Page | pp. 285 - 290 |
| Keyword | backhopping, caches, error-correcting code, STT-RAM |
| Abstract | Recent researches on STT-RAM revealed that device scaling makes its write operations unreliable. To mitigate the impact of this problem, this paper proposes a low-cost, ECC-based solution for STT-RAM caches. In particular, it proposes to share storage for ECC among different blocks within a set and to use them only for unsuccessful write operations. Experimental results show that our scheme reduces 74% to 98% of area overhead incurred by the conventional per-block ECC while maintaining system performance and reliability. |
| Title | Loadsa: A Yield-Driven Top-Down Design Method for STT-RAM Array |
| Author | Wujie Wen, Yaojun Zhang, Lu Zhang, *Yiran Chen (University of Pittsburgh, U.S.A.) |
| Page | pp. 291 - 296 |
| Keyword | Yield-driven, Top-down, Statistical design, STT-RAM |
| Abstract | As an emerging nonvolatile memory technology, spin transfer torque random access memory (STT-RAM) faces great design challenges. The large device variations and the thermal induced switching randomness of the magnetic tunneling junction(MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system designs. Also, the conventional bottom-up design method incurs costly iterations in the STT-RAM design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven top-down design method to explore the design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a top-down design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array and cell-level design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that "Loadsa" can accurately optimize the STT-RAM based on the system and cell level constraints with a linear computation complexity. Our method demonstrates great potentials in the early design stage of memory or micro-architecture by eliminating the design integrations, while offering a full statistical view of the design even when the common yield enhancement practices are applied. |
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