| Title | (Invited Paper) Challenges in Integration of Diverse Functionalities on CMOS |
| Author | *Kazuya Masu, Noboru Ishihara (Tokyo Institute of Technology, Japan), Toshifumi Konishi (NTT Advanced Technology, Japan), Katsuyuki Machida (Tokyo Institute of Technology, Japan), Hiroshi Toshiyoshi (The University of Tokyo, Japan) |
| Page | pp. 390 - 393 |
| Abstract | We introduce “Wafer Shuttle” that is suitable for integration of diverse functionalities. CMOS/MEMS design flow and environment based on SPICE is discussed. It is pointed out that modeling will be important to promote the R&D of MEMS/CMOS and/or diverse-functionalities integration on CMOS. |
| Title | (Invited Paper) 3DIC from Concept to Reality |
| Author | Frank Lee, Bill Shen, Willy Chen, *Suk Lee (Taiwan Semiconductor Manufacturing Company, Taiwan) |
| Page | pp. 394 - 398 |
| Keyword | 3DIC, TSMC, System, Design |
| Abstract | 3DIC technology presents a new system integration strategy for the electronics industry to achieve superior system performance with lower power consumption, higher bandwidth, smaller system form factor, and shorter time to market through heterogeneous integration. TSMC's “Chip-on-Wafer-on-Substrate (CoWoS)” technology opens up a new opportunity to bring 3D chip stacking vision from concept to reality. The provided methodology will be discussed about this market trend and the different pieces needed to jointly make it a success, which includes customers' required applications, TSMC's support design flow, as well as the ecosystem design enablement of multi-die implementation, DFT solution, thermal analysis, verification and new categories of IPs. |
| Title | (Invited Paper) 2.5D Design Methodology |
| Author | *Sinya Tokunaga (Semiconductor Technology Academic Research Center, Japan) |
| Page | pp. 399 - 402 |
| Keyword | 3D-IC, Silicon interposer, TSV, Co-design, Co-analysis |
| Abstract | We present about 2.5D design methodology. Very important issue is a high frequency insertion loss on the silicon interposer. There are two wiring methodologies on the silicon interposer. One is the Manhattan wiring method like as LSI wiring design and the other is the transmission channel wiring method like as package design. We have confirmed that the transmission channel wiring is twice better electro characteristic than the Manhattan wiring using a component model that is 6mm length at 1 GHz. |
| Title | (Invited Paper) Design Issues in Heterogeneous 3D/2.5D Integration |
| Author | *Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne (IMEC, Belgium) |
| Page | pp. 403 - 410 |
| Keyword | Heterogeneous, 3D/2.5D Integration, Thermal, mechanical analysis, Design for test |
| Abstract | Efficient processing of fine-pitched Through Silicon Vias, micro-bumps and back-side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows typically conceived for 2D systems. With all system, technology and implementation level options brought with these features, the design space increases to an extent where traditional 2D tools cannot be used any more for efficient exploration. Therefore, the cost-effective design of future 3D ICs products will require new planning and co-optimisation techniques and tools that are fast and accurate enough to cope with these challenges. In this paper we present design methodology and the practical EDA tool chain that covers different aspects of the design flow and is specific to efficient design of 3D-ICs. Flow features include: fast synthesis and 3D design partitioning at gate level, TSV/micro-bump array planning, 3D floor planning, placement and routing, congestion analysis, fast thermal and mechanical modeling, easy technology vs. implementation trade-off analysis, 3D device models generations and Design-for-Test (DfT). The application of the tool chain is illustrated using concrete example of a real-world design, showing not only the applicability of the tool chain, but also the benefits of heterogeneous 2.5 and 3D integration technologies. |