| Title | HS3DPG: Hierarchical Simulation for 3D P/G Network |
| Author | *Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma (Tsinghua University, China), Yiyu Shi (Missouri University of Science and Technology, U.S.A.), Hui Wang, Huazhong Yang (Tsinghua University, China) |
| Page | pp. 509 - 514 |
| Keyword | 3D P/G network, hierarchical simulation, port equivalent model |
| Abstract | As different chips are stacked together in 3D ICs, the power/ground (P/G) network simulation becomes more challenging than that of 2D cases. In this paper, we propose a hierarchical simulation method suitable for 3D P/G network (HS3DPG), which can ensure full parallelism and good scalability with the number of tiers. Besides, the "locality" property is introduced into HS3DPG to further simplify the simulation. Finally, we use HS3DPG to analyze the voltage distribution of a 3D P/G network with clustered TSVs. |
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| Title | Piecewise-Polynomial Associated Transform Macromodeling Algorithm for Fast Nonlinear Circuit Simulation |
| Author | *Yang Zhang, Neric Fong, Ngai Wong (The University of Hong Kong, Hong Kong) |
| Page | pp. 515 - 520 |
| Keyword | Nonlinear MOR, Associated transform, TPWL, PWP, Macromodeling |
| Abstract | We present a piecewise-polynomial based associated transform algorithm (PWPAT) for macromodeling nonlinear circuits in system-level circuit design. The generated reduced model can provide both global and local accuracies with the most compact dimension. Numerical examples compare it with existing algorithms and verify its superior accuracy in higher order harmonics simulation over traditional Trajectory Piecewise-Linear (TPWL) approach. |
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| Title | An Ultra-Compact Virtual Source FET Model for Deeply-Scaled Devices: Parameter Extraction and Validation for Standard Cell Libraries and Digital Circuits |
| Author | *Li Yu, Omar Mysore, Lan Wei, Luca Daniel, Dimitri Antoniadis (MIT, U.S.A.), Ibrahim Elfadel (Masdar Institute of Science and Technology, United Arab Emirates), Duane Boning (MIT, U.S.A.) |
| Page | pp. 521 - 526 |
| Keyword | ultra-compact model, parameter extraction, library cell characterization, VLSI timing, power analysis |
| Abstract | In this paper, we present the first validation of the virtual source(VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40nm bulk silicon model. The VS model is used to fully characterize a standard cell library at the 40nm node with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6*. |
| Title | On Potential Design Impacts of Electromigration Awareness |
| Author | Andrew B. Kahng, *Siddhartha Nath, Tajana S. Rosing (University of California, San Diego, U.S.A.) |
| Page | pp. 527 - 532 |
| Keyword | Electromgration, Fmax, EM slack, tradeoff, reliability |
| Abstract | Reliability issues significantly limit performance improvements from Moore’s-Law scaling. At 45nm and below, electromigration (EM) is a serious reliability issue which affects global and local interconnects in a chip and limits performance scaling. Traditional IC implementation flows meet a 10-year lifetime requirement by overdesigning and sacrificing performance. At the same time, it is well-known among circuit designers that Black’s Equation [2] suggests that lifetime can be traded for performance. In our work, we carefully study the impacts of EM-awareness on IC implementation outcomes, and show that circuit performance does not trade off so smoothly with mean time to failure (MTTF) as suggested by Black’s Equation. We conduct two basic studies: EM lifetime versus performance with fixed resource budget, and EM lifetime versus resource with fixed performance. Using design examples implemented in two process nodes, we show that performance scaling achieved by reducing the EM lifetime requirement depends on the EM slack in the circuit, which in turn depends on factors such as timing constraints, length of critical paths and the mix of cell sizes. Depending on these factors, the performance gain can range from 10% to 80% when the lifetime requirement is reduced from 10 years to one year. We show that at a fixed performance requirement, power and area resources are affected by the timing slack and can either decrease by 3% or increase by 7.8% when the MTTF requirement is reduced. We also study how conventional EM fixes using per net Non-Default Rule (NDR) routing, downsizing of drivers, and fanout reduction affect performance at reduced lifetime requirements. Our study indicates, e.g., that NDR routing can increase performance by up to 5% but at the cost of 2% increase in area at a reduced 7-year lifetime requirement. |
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