| Title | Provably Optimal Test Cube Generation using Quantified Boolean Formula Solving |
| Author | Matthias Sauer, *Sven Reimer (University of Freiburg, Germany), Ilia Polian (University of Passau, Germany), Tobias Schubert, Bernd Becker (University of Freiburg, Germany) |
| Page | pp. 533 - 539 |
| Keyword | Test Cube, X-input, QBF, SAT, Relaxation |
| Abstract | Circuits that employ test pattern compression rely on test cubes to achieve high compression ratios. The less inputs of a test pattern are specified,
the better it can be compacted and hence the lower
the test application time. Although there exist previous
approaches to generate such test cubes, none of them
are optimal. We present for the first time a framework
that yields provably optimal test cubes by using the
theory of quantified Boolean formulas (QBF). Extensive comparisons with previous methods demonstrate
the quality gain of the proposed method. |
| Slides |
| Title | Synthesizing Multiple Scan Chains by Cost-Driven Spectral Ordering |
| Author | *Louis Y.-Z. Lin, Christina C.-H. Liao, Charles H.-P. Wen (Dept. of Elec. & Comp. engr., National Chiao Tung University, Taiwan) |
| Page | pp. 540 - 545 |
| Keyword | testing, scan chain, scan order |
| Abstract | Power cost and wire cost are two most critical issues in scan-chain optimization for modern VLSI testing.
Many previous works used layout-based partitioning and
greedy heuristics to synthesize multiple scan chains, making themselves suffer from (1) nongeometric-cost problem and
(2) crossing-edge problem. Therefore, in this paper, we
propose cost-driven spectral ordering including (1) cost-driven k-way spectral partitioning and (2) greedy non-crossing 2-opt ordering to resolve the two problems stated above, respectively. Experiments show that different cost metrics
can be properly addressed in k-way spectral partitioning.
Moreover, our cost-driven spectral ordering achieves on average
9% mixed (power-and-wire) reduction than two previous works on benchmark circuits, which evidently demonstrates its effectiveness on multiple scan-chain synthesis. |
| Title | Full Exploitation of Process Variation Space for Continuous Delivery of Optimal Delay Test Quality |
| Author | Baris Arslan (University of California, San Diego/Qualcomm, U.S.A.), *Alex Orailoglu (University of California, San Diego, U.S.A.) |
| Page | pp. 552 - 557 |
| Keyword | delay test, test cost optimization, adaptive test, process-aware test |
| Abstract | The increasing magnitude of process variations individualizes effectively each chip, necessitating distinct quantities of test resources for each in order to optimize overall delay test quality without exceeding set test budgets. This paper proposes an analytical framework that delivers the optimal test time assignment per chip in order to minimize the delay defect escape rate. Adjustment of the chip-specific test time in the continuous process variation space is attained through an adaptive test flow that utilizes process data measurements from the device under test. The results evince that a substantial improvement in the delay test quality can be obtained at no increase whatsoever to test time consumed by conventional test flows. |