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The 18th Asia and South Pacific Design Automation Conference

Session 7B  Simulation Acceleration
Time: 10:20 - 12:20 Friday, January 25, 2013
Chairs: Farhad Mehdipour (Kyushu Univ., Japan), Antoine Trouve (ISIT, Japan)

7B-1 (Time: 10:20 - 10:50)
TitleNative Simulation of Complex VLIW Instruction Sets using Static Binary Translation and Hardware-Assisted Virtualization
Author*Mian-Muhammad Hamayun, Frédéric Pétrot, Nicolas Fournel (TIMA Laboratory, CNRS/INP Grenoble/UJF, France)
Pagepp. 576 - 581
Detailed information (abstract, keywords, etc)

7B-2 (Time: 10:50 - 11:20)
TitleRExCache: Rapid Exploration of Unified Last-level Cache
Author*Su Myat Min Shwe, Haris Javaid, Sri Parameswaran (Univ. of New South Wales, Australia)
Pagepp. 582 - 587
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7B-3 (Time: 11:20 - 11:50)
TitleAn Efficient Hybrid Synchronization Technique for Scalable Multi-Core Instruction Set Simulations
Author*Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 588 - 593
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